公开(公告)号：US20190355516A1

公开(公告)日：2019-11-21

申请号：US16527170

申请日：2019-07-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takehito Ishihara ,  Noriyuki Inoue ,  Tatsuya Funaki

IPC: H01G4/12 ,  H01L21/822 ,  H01L27/04 ,  H01G4/005 ,  H01G4/33 ,  H01G9/00 ,  H01G9/07 ,  H01L49/02

Abstract: A capacitor is provided that includes an electrostatic capacitance forming portion with a first electrode/dielectric layer/second electrode structure, and a silicon portion. Moreover, the silicon portion is disposed on at least a part of a side of the electrostatic capacitance forming portion. When the capacitor is viewed in a thickness direction thereof, a region occupied by the silicon portion in a lower portion of the electrostatic capacitance forming portion is 50% or less.

公开(公告)号：US11646155B2

公开(公告)日：2023-05-09

申请号：US17344666

申请日：2021-06-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takehito Ishihara ,  Tatsuya Funaki ,  Haruhiko Ikeda

IPC: H01G4/005 ,  H01G4/224

CPC classification number: H01G4/005 ,  H01G4/224

Abstract: An electrode-equipped passive component is an electrode-equipped passive component to be mounted on a mount target, and includes a passive component main body, an electrode provided on a mount surface of the passive component main body, and an underfill layer provided on the mount surface of the passive component main body. The underfill layer includes a thermosetting resin, a flux, and a solvent, and has a surface having a skin layer. The skin layer has tack power equal to or smaller than 25 mN/mm2 at room temperature and equal to or larger than 60 mN/mm2 at 40° C.

公开(公告)号：US20220020692A1

公开(公告)日：2022-01-20

申请号：US17490424

申请日：2021-09-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tatsuya Funaki ,  Shunsuke Abe

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/29 ,  H01L21/48 ,  H01L21/56

Abstract: A composite component that includes an interposer structure and an electronic component. The interposer structure includes a Si base layer having a first main surface and a second main surface facing each other, a rewiring layer on the first main surface, a through Si via electrically connected to the rewiring layer and penetrating the Si base layer, an interposer electrode facing the second main surface, and an adhesive layer. The electronic component has a surface and a component electrode on the surface and connected to the through Si via, and is located between the interposer electrode and the Si base layer such that the component electrode and the surface are adhered to the second main surface of the Si base layer with the adhesive layer interposed therebetween. The through Si via extends from the second main surface, penetrates the adhesive layer, and is electrically connected to the component electrode.

公开(公告)号：US20200321323A1

公开(公告)日：2020-10-08

申请号：US16907557

申请日：2020-06-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koshi Himeda ,  Tatsuya Kitamura ,  Chiharu Sakaki ,  Shinya Kiyono ,  Sho Fujita ,  Atsushi Yamamoto ,  Takeshi Furukawa ,  Kenji Nishiyama ,  Tatsuya Funaki ,  Kinya Aoki

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.

公开(公告)号：US20190074347A1

公开(公告)日：2019-03-07

申请号：US16176506

申请日：2018-10-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tatsuya Funaki ,  Noriyuki Inoue

IPC: H01L49/02 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/12 ,  H01L21/56 ,  H01G4/12 ,  H01G4/33

Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.

公开(公告)号：US12154709B2

公开(公告)日：2024-11-26

申请号：US17350624

申请日：2021-06-17

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yoshimasa Yoshioka ,  Tatsuya Funaki ,  Shunsuke Abe

IPC: H01F27/28 ,  H01F27/06 ,  H01F27/32 ,  H01F41/04 ,  H01F41/12

Abstract: A surface-mount passive component includes a passive element and a size conversion unit on which the passive element is mounted. The size conversion unit has a body, a plurality of first external terminals each of which is exposed on an element mount surface of the body and is electrically connected to a corresponding one of passive element external terminals of the passive element, a plurality of second external terminals exposed on a board-side mount surface of the body, and connection wires that electrically connect the first external terminals and the second external terminals. An area of the board-side mount surface is larger than an area of a first main surface of the passive element, and a total area of the plurality of second external terminals on the board-side mount surface is larger than a total area of the passive element external terminals on the first main surface.

公开(公告)号：US11552020B2

公开(公告)日：2023-01-10

申请号：US17398574

申请日：2021-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koshi Himeda ,  Tatsuya Kitamura ,  Chiharu Sakaki ,  Shinya Kiyono ,  Sho Fujita ,  Atsushi Yamamoto ,  Takeshi Furukawa ,  Kenji Nishiyama ,  Tatsuya Funaki ,  Kinya Aoki

IPC: H05K1/02 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16 ,  H02M3/00

Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.

公开(公告)号：US11348726B2

公开(公告)日：2022-05-31

申请号：US16527170

申请日：2019-07-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takehito Ishihara ,  Noriyuki Inoue ,  Tatsuya Funaki

IPC: H01G4/005 ,  H01G4/33 ,  H01G9/07 ,  H01L49/02

Abstract: A capacitor is provided that includes an electrostatic capacitance forming portion with a first electrode/dielectric layer/second electrode structure, and a silicon portion. Moreover, the silicon portion is disposed on at least a part of a side of the electrostatic capacitance forming portion. When the capacitor is viewed in a thickness direction thereof, a region occupied by the silicon portion in a lower portion of the electrostatic capacitance forming portion is 50% or less.

公开(公告)号：US20210375841A1

公开(公告)日：2021-12-02

申请号：US17398574

申请日：2021-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koshi Himeda ,  Tatsuya Kitamura ,  Chiharu Sakaki ,  Shinya Kiyono ,  Sho Fujita ,  Atsushi Yamamoto ,  Takeshi Furukawa ,  Kenji Nishiyama ,  Tatsuya Funaki ,  Kinya Aoki

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498

Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.

公开(公告)号：US10727295B2

公开(公告)日：2020-07-28

申请号：US16176506

申请日：2018-10-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tatsuya Funaki ,  Noriyuki Inoue

IPC: H01L29/00 ,  H01L49/02 ,  H01G4/33 ,  H01G4/12 ,  H01L21/56 ,  H01L23/525 ,  H01L23/522 ,  H01L23/00 ,  H01L23/12 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

Abstract: A wafer level package which includes an IC chip; a rewiring layer on the IC chip; and a capacitor embedded in the rewiring layer.