公开(公告)号：US11121123B2

公开(公告)日：2021-09-14

申请号：US16907557

申请日：2020-06-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koshi Himeda ,  Tatsuya Kitamura ,  Chiharu Sakaki ,  Shinya Kiyono ,  Sho Fujita ,  Atsushi Yamamoto ,  Takeshi Furukawa ,  Kenji Nishiyama ,  Tatsuya Funaki ,  Kinya Aoki

IPC: H05K3/46 ,  H01L25/16 ,  H01L21/48 ,  H01L23/498 ,  H02M3/00

Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.

公开(公告)号：US12009273B2

公开(公告)日：2024-06-11

申请号：US16749886

申请日：2020-01-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi Kurokawa ,  Koshi Himeda ,  Kazuya Kobayashi

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/082 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/737

CPC classification number: H01L23/367 ,  H01L23/528 ,  H01L24/13 ,  H01L27/0207 ,  H01L27/082 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/205 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/452 ,  H01L29/7371

Abstract: A semiconductor apparatus includes a substrate, plural transistor groups disposed on the substrate, an insulating film, and a metal member. Each of the plural transistor groups includes plural unit transistors arranged in a first direction within a plane of a top surface of the substrate. The plural transistor groups are arranged in a second direction perpendicular to the first direction. The insulating film covers the plural unit transistors and includes at least one cavity. The metal member is disposed on the insulating film and is electrically connected to the plural unit transistors via the at least one cavity. A heat transfer path is formed by a metal in a region from each of the plural unit transistors to a top surface of the metal member. Thermal resistance values of the heat transfer paths are different from each other among the plural unit transistors.

公开(公告)号：US11817493B2

公开(公告)日：2023-11-14

申请号：US17545973

申请日：2021-12-08

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Mari Saji ,  Atsushi Kurokawa ,  Koshi Himeda

IPC: H01L29/737 ,  H01L23/00 ,  H01L29/66

CPC classification number: H01L29/737 ,  H01L24/13 ,  H01L29/66242 ,  H01L29/66318 ,  H01L2224/0401

Abstract: A semiconductor device includes a substrate having an upper surface on which are arranged first transistors each including a mesa structure formed of a semiconductor. A first bump having a shape elongated in one direction in plan view and connected to the first transistors is arranged at a position overlapping the first transistors in plan view. A second bump has a space with respect to the first bump in a direction orthogonal to a longitudinal direction of the first bump. A first metal pattern is arranged between the first and second bumps in plan view. When the upper surface of the substrate is taken as a height reference, a center of the first metal pattern in a thickness direction has a height higher than an upper surface of the mesa structure included in each of the first transistors and lower than a lower surface of the first bump.

公开(公告)号：US11863128B2

公开(公告)日：2024-01-02

申请号：US17167406

申请日：2021-02-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Hideyuki Sato ,  Koshi Himeda

IPC: H03F1/30 ,  H03F1/08 ,  H03F3/213 ,  H01L27/102 ,  H01L29/737 ,  H01L23/00

CPC classification number: H03F1/08 ,  H01L24/13 ,  H01L27/1022 ,  H01L29/7371 ,  H03F3/213 ,  H01L2224/13025 ,  H01L2924/13051 ,  H01L2924/1421 ,  H03F2200/447 ,  H03F2200/451

Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor that supplies a bias current based on a first current which is a part of a control current to the first transistor; a current output element in which a current flowing therethrough increases in accordance with a rise in temperature; and a wiring portion including a plurality of metal layers that are electrically connected to an emitter of the first transistor and that are stacked one on top of another so as to oppose the semiconductor substrate. At least one metal layer among the plurality of metal layers extends so as to overlap an area extending from at least a part of a first disposition area in which the first transistor is disposed to a second disposition area in which the current output element is disposed in plan view of the semiconductor substrate.

公开(公告)号：US11552020B2

公开(公告)日：2023-01-10

申请号：US17398574

申请日：2021-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koshi Himeda ,  Tatsuya Kitamura ,  Chiharu Sakaki ,  Shinya Kiyono ,  Sho Fujita ,  Atsushi Yamamoto ,  Takeshi Furukawa ,  Kenji Nishiyama ,  Tatsuya Funaki ,  Kinya Aoki

IPC: H05K1/02 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16 ,  H02M3/00

Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.

公开(公告)号：US11515442B2

公开(公告)日：2022-11-29

申请号：US17062461

申请日：2020-10-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Fujimoto ,  Koshi Himeda ,  Toshihiro Tada ,  Tetsuro Toritsuka ,  Shinji Kaburaki

IPC: H01L31/10 ,  H01S5/042 ,  H01S5/028 ,  H01S5/227

Abstract: An optical semiconductor element having a mesa portion includes a substrate and semiconductor layers on the substrate. The optical semiconductor element further includes a first contact electrode, a second contact electrode on the semiconductor layer, first and second lead-out wires connected to the first and second contact electrodes, respectively, and an insulating film covering at least an upper surface of the semiconductor layer and the second contact electrode. The second lead-out wire is connected to the second contact electrode in an opening of the insulating film. An outer peripheral end of the second contact electrode in at least a portion where the second contact electrode and the second lead-out wire are connected is above and outside an outer peripheral end of a connection portion with the semiconductor layer, and an inner peripheral end is above and inside an inner peripheral end of the connection portion with the semiconductor layer.

公开(公告)号：US20240355532A1

公开(公告)日：2024-10-24

申请号：US18761609

申请日：2024-07-02

Applicant: Murata Manufacturing Co,. Ltd.

Inventor： Yoshimitsu USHIMI ,  Koshi Himeda ,  Kenji Nishiyama ,  Hidehiko Sasaki ,  Nobuyoshi Adachi

IPC: H01F27/28 ,  H01F27/24

CPC classification number: H01F27/2823 ,  H01F27/24

Abstract: A coil that includes a coil wire spirally wound along an axis. The coil wire includes a first wiring portion and a second wiring portion which are aligned along the axis. The first wiring portion includes a first end surface on a side in a first direction from the first wiring portion toward the second wiring portion, and a second end surface on a side in a second direction opposite to the first direction. The first end surface includes a first end in an inner side portion in a radial direction of the coil wire. The second end surface is in an outer side portion in the radial direction of the coil wire with respect to a straight line passing through the first end and parallel to the direction of the axis.

公开(公告)号：US20210375841A1

公开(公告)日：2021-12-02

申请号：US17398574

申请日：2021-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koshi Himeda ,  Tatsuya Kitamura ,  Chiharu Sakaki ,  Shinya Kiyono ,  Sho Fujita ,  Atsushi Yamamoto ,  Takeshi Furukawa ,  Kenji Nishiyama ,  Tatsuya Funaki ,  Kinya Aoki

IPC: H01L25/16 ,  H01L21/48 ,  H01L23/498

Abstract: A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.

公开(公告)号：US10777667B2

公开(公告)日：2020-09-15

申请号：US16681640

申请日：2019-11-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Atsushi Kurokawa ,  Koshi Himeda ,  Kazuya Kobayashi

IPC: H01L29/73 ,  H01L29/732 ,  H01L23/31 ,  H01L23/00 ,  H01L29/417

Abstract: A semiconductor device has bipolar transistors on a substrate. There is also an insulating film on the substrate, covering the bipolar transistors. On this insulating film is emitter wiring, sticking through openings in the insulating film (first openings) to be electrically coupled to the emitter layer of the bipolar transistors. On the emitter wiring is a protective film. On the protective film is a bump, sticking through an opening in the protective film (second opening) to be electrically coupled to the emitter wiring. In plan view, the second opening is included in the area that is inside the bump and outside the first openings.

公开(公告)号：US12278197B2

公开(公告)日：2025-04-15

申请号：US17718725

申请日：2022-04-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Nishiyama ,  Koshi Himeda ,  Yoshimitsu Ushimi

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02

Abstract: A package board that includes an inductor layer having: a first magnetic layer including first magnetic particles and a resin; an inductor wiring that functions as an inductor in the first magnetic layer; and a second magnetic layer on at least one surface of the first magnetic layer, including second magnetic particles that are higher in average flatness than the first magnetic particles and a resin, the second magnetic particles having a shape where the dimension in a direction along the main surface of the second magnetic layer is longer than the dimension in the thickness direction of the second magnetic layer.