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11 条记录 (耗时 0.039 秒)

    INSPECTING APPARATUS FOR SOLAR CELL AND INSPECTING METHOD USING THE SAME
    2.
    发明申请
    INSPECTING APPARATUS FOR SOLAR CELL AND INSPECTING METHOD USING THE SAME 失效
    用于太阳能电池的检查装置和使用它的检查方法

    公开(公告)号：US20100060305A1

    公开(公告)日：2010-03-11

    申请号：US12505364

    申请日：2009-07-17

    申请人： Myung-Hun SHIN ,  Min-Seok OH ,  Ku-Hyun KANG ,  Yuk-Hyun NAM ,  Seung-Jae JUNG ,  Min PARK

    发明人： Myung-Hun SHIN ,  Min-Seok OH ,  Ku-Hyun KANG ,  Yuk-Hyun NAM ,  Seung-Jae JUNG ,  Min PARK

    IPC分类号： G01R31/02

    CPC分类号： H02S50/10

    摘要： An inspecting apparatus for a solar cell and an inspecting method are provided. The inspecting apparatus for the solar cell includes a head unit having a plurality of probe units, a rotation unit rotating the head unit according to an interval of cells of the solar cell, a controller controlling a rotation angle of the head unit by controlling the rotation unit, and a wire unit connected to the head unit to be electrically connected to the probe units.

    摘要翻译： 提供了一种用于太阳能电池的检查装置和检查方法。 用于太阳能电池的检查装置包括具有多个探针单元的头单元，按照太阳能电池单元的间隔旋转头单元的旋转单元，通过控制旋转来控制头单元的旋转角度的控制器 单元和连接到头单元的导线单元以电连接到探针单元。

    PHOTOELECTRIC CONVERSION DEVICE
    6.
    发明申请
    PHOTOELECTRIC CONVERSION DEVICE 审中-公开
    光电转换器件

    公开(公告)号：US20120280232A1

    公开(公告)日：2012-11-08

    申请号：US13411661

    申请日：2012-03-05

    申请人： Seung-Jae JUNG ,  Yuk-Hyun NAM ,  Ki-Won Jeon

    发明人： Seung-Jae JUNG ,  Yuk-Hyun NAM ,  Ki-Won Jeon

    IPC分类号： H01L31/0376

    CPC分类号： H01L31/028 ,  H01L31/076 ,  Y02E10/547 ,  Y02E10/548

    摘要： A photoelectric conversion device includes a first photoelectric conversion unit on a substrate and having a first energy bandgap, a second photoelectric conversion unit having a second energy bandgap that is different from the first energy bandgap, the second photoelectric conversion unit being on the first photoelectric conversion unit, and an intermediate unit between the first and second photoelectric conversion units, the intermediate unit including a stack of a first intermediate layer and a second intermediate layer, each of the first intermediate layer and the second intermediate layer having a refractive index that is smaller than that of the first photoelectric conversion unit, the first intermediate layer having a first refractive index, and the second intermediate layer having a second refractive index that is smaller than the first refractive index.

    摘要翻译： 光电转换装置包括在基板上具有第一能带隙的第一光电转换单元，具有与第一能带隙不同的第二能带隙的第二光电转换单元，第二光电转换单元处于第一光电转换 单元和第一和第二光电转换单元之间的中间单元，所述中间单元包括第一中间层和第二中间层的堆叠，所述第一中间层和所述第二中间层中的每一个具有较小的折射率 第一中间层具有第一折射率，第二中间层的第二折射率小于第一折射率。

    METHOD FOR DESIGNING AND MANUFACTURING AN INTEGRATED CIRCUIT, SYSTEM FOR CARRYING OUT THE METHOD, AND SYSTEM FOR VERIFYING AN INTEGRATED CIRCUIT
    7.
    发明申请
    METHOD FOR DESIGNING AND MANUFACTURING AN INTEGRATED CIRCUIT, SYSTEM FOR CARRYING OUT THE METHOD, AND SYSTEM FOR VERIFYING AN INTEGRATED CIRCUIT 有权
    用于设计和制造集成电路的方法，用于实现该方法的系统和用于验证集成电路的系统

    公开(公告)号：US20150302135A1

    公开(公告)日：2015-10-22

    申请号：US14690227

    申请日：2015-04-17

    申请人： Chul-Hong PARK ,  Sang-Hoon BAEK ,  Su-Hyeon KIM ,  Kyoung-Yun BAEK ,  Sung-Wook AHN ,  Sang-Kyu OH ,  Seung-Jae JUNG

    发明人： Chul-Hong PARK ,  Sang-Hoon BAEK ,  Su-Hyeon KIM ,  Kyoung-Yun BAEK ,  Sung-Wook AHN ,  Sang-Kyu OH ,  Seung-Jae JUNG

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G06F17/5072

    摘要： A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

    摘要翻译： 集成电路的制造方法，用于实施该方法的系统以及用于验证集成电路的系统可以使用包括可能违反设计规则的第一布局区域的标准单元布局。 用于设计集成电路的方法可以包括接收包括缩放增强电路布局的数据文件，以及使用设计规则和数据文件来设计第一标准单元布局。 设计第一标准单元布局可以包括使用数据文件设计第一标准单元布局的第一布局区域，以及使用设计规则设计第一标准单元布局的第二区域。

    THIN FILM SOLAR CELL
    8.
    发明申请
    THIN FILM SOLAR CELL 审中-公开
    薄膜太阳能电池

    公开(公告)号：US20110067756A1

    公开(公告)日：2011-03-24

    申请号：US12862959

    申请日：2010-08-25

    申请人： Seung-Jae JUNG

    发明人： Seung-Jae JUNG

    IPC分类号： H01L31/0376

    CPC分类号： H01L31/076 ,  H01L31/0352 ,  H01L31/03685 ,  H01L31/03762 ,  H01L31/03765 ,  H01L31/0547 ,  H01L31/056 ,  Y02E10/52 ,  Y02E10/545 ,  Y02E10/548

    摘要： A thin film solar cell includes; a first electrode, a first active layer disposed on the first electrode, a porous intermediate layer disposed on the first active layer, a second active layer disposed on the intermediate layer and a second electrode disposed on the second active layer.

    摘要翻译： 薄膜太阳能电池包括： 第一电极，设置在第一电极上的第一有源层，设置在第一有源层上的多孔中间层，设置在中间层上的第二有源层和设置在第二有源层上的第二电极。

    VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    9.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    可变电阻存储器件及其制造方法

    公开(公告)号：US20160197121A1

    公开(公告)日：2016-07-07

    申请号：US14984477

    申请日：2015-12-30

    申请人： Jin-Woo LEE ,  Youn-Sean KANG ,  Seung-Jae JUNG ,  Hyun-Su JU ,  Masayuki TERAI

    发明人： Jin-Woo LEE ,  Youn-Sean KANG ,  Seung-Jae JUNG ,  Hyun-Su JU ,  Masayuki TERAI

    IPC分类号： H01L27/24 ,  H01L43/08 ,  H01L43/02 ,  H01L45/00 ,  H01L27/22

    CPC分类号： H01L27/2463 ,  H01L27/224 ,  H01L27/2409 ,  H01L43/12 ,  H01L45/1675

    摘要： A variable resistance memory device includes a plurality of first conductive layer pattern, a plurality of second conductive layer patterns over the first conductive layer patterns, and a plurality of lower cell structures including a switching element and a variable resistance element, the lower cell structures being formed at intersections at which the first conductive layer patterns and the second conductive layer patterns overlap each other. The first conductive layer patterns, the second conductive layer patterns and the lower cell structures serves as one of a memory cell, a first dummy pattern structure and a second dummy pattern structure. The first dummy pattern structure is formed on both edge portions in the first direction, and the second conductive layer pattern of the first dummy pattern structure protrudes in the first direction from a sidewall of the lower cell structure thereunder, and the second dummy pattern structure is formed on both edge portions in the second direction, and the first conductive layer pattern of the second dummy pattern structure protrudes in the second direction from a sidewall of the lower cell structure thereon. Failures of the variable resistance memory device due to the etch residue may decrease.

    摘要翻译： 可变电阻存储器件包括多个第一导电层图案，多个第一导电层图案上的第二导电层图案，以及包括开关元件和可变电阻元件的多个下单元结构，下单元结构为 形成在第一导电层图案和第二导电层图案彼此重叠的交点处。 第一导电层图案，第二导电层图案和下单元结构用作存储单元，第一虚设图案结构和第二虚设图案结构之一。 第一虚设图形结构形成在第一方向的两个边缘部分上，第一虚设图案结构的第二导电层图案从其下部单元结构的侧壁沿第一方向突出，第二虚设图案结构为 形成在第二方向的两个边缘部分上，并且第二虚设图案结构的第一导电层图案在其下面的单元结构的侧壁上沿第二方向突出。 由于蚀刻残留导致的可变电阻存储器件的故障可能降低。

    VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    10.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
    可变电阻存储器件及其制造方法

    公开(公告)号：US20160027845A1

    公开(公告)日：2016-01-28

    申请号：US14682506

    申请日：2015-04-09

    申请人： Dong-Jun SEONG ,  Youn-Seon KANG ,  Seung-Jae JUNG ,  Jung-Dal CHOI

    发明人： Dong-Jun SEONG ,  Youn-Seon KANG ,  Seung-Jae JUNG ,  Jung-Dal CHOI

    IPC分类号： H01L27/24 ,  H01L45/00

    CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

    摘要： A variable resistance memory device, and methods of manufacturing the same, include a plurality of first conductive structures extending in a first direction, a plurality of second conductive structures extending in a second direction crossing the first direction over the first conductive structures, the second conductive structures, and a plurality of memory cells that are formed at intersections at which the first conductive structures and the second conductive structures overlap each other, and each includes a selection element and a variable resistance element sequentially stacked. An upper surface of each of the first conductive structures has a width in the second direction less than a width of a bottom surface of each of the selection elements.

    摘要翻译： 可变电阻存储器件及其制造方法包括沿第一方向延伸的多个第一导电结构，沿与第一导电结构相交的第一方向的第二方向延伸的多个第二导电结构，第二导电 结构和形成在第一导电结构和第二导电结构彼此重叠的交点处的多个存储单元，并且每个存储单元包括依次堆叠的选择元件和可变电阻元件。 每个第一导电结构的上表面在第二方向上的宽度小于每个选择元件的底表面的宽度。