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    Magnetic-domain-wall-displacement memory cell and initializing method therefor
    2.
    发明授权
    Magnetic-domain-wall-displacement memory cell and initializing method therefor 有权
    磁畴壁位移记忆单元及其初始化方法

    公开(公告)号：US09478309B2

    公开(公告)日：2016-10-25

    申请号：US14437197

    申请日：2013-09-13

    申请人： NEC Corporation ,  TOHOKU UNIVERSITY

    发明人： Ryusuke Nebashi ,  Noboru Sakimura ,  Tadahiko Sugibayashi ,  Yukihide Tsuji ,  Ayuka Tada ,  Hiroaki Honjou ,  Hideo Ohno

    IPC分类号： G11C19/08 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  G11C11/18

    CPC分类号： G11C19/0833 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1697 ,  G11C11/18 ,  H01L43/02 ,  H01L43/08

    摘要： Provided is a magnetic domain wall displacement memory cell, including a recording layer including a magnetic film, the recording layer including: a magnetization reversal region in which magnetization is reversible; and first and second magnetization fixed regions that supply a spin-polarized electron to the magnetization reversal region. The magnetic domain wall displacement memory cell is configured so that a first region in which magnetization reversal occurs due to a first current flowing in a direction parallel to a film surface of the recording layer and a first magnetic field component in the direction parallel to the film surface of the recording layer is formed, and a second region in which no magnetization reversal occurs is formed.

    摘要翻译： 提供一种磁畴壁位移存储单元，其包括包括磁性膜的记录层，所述记录层包括：磁化反转区域，其中磁化是可逆的; 以及向磁化反转区域提供自旋极化电子的第一和第二磁化固定区域。 磁畴壁位移存储单元被配置为使得由于在与记录层的膜表面平行的方向上流动的第一电流而产生磁化反转的第一区域和与该膜平行的方向上的第一磁场分量 形成记录层的表面，形成没有发生磁化反转的第二区域。

    NONVOLATILE LOGIC GATE DEVICE
    3.
    发明申请
    NONVOLATILE LOGIC GATE DEVICE 有权
    非诺基亚门电路设备

    公开(公告)号：US20150138877A1

    公开(公告)日：2015-05-21

    申请号：US14400950

    申请日：2013-05-15

    申请人： NEC CORPORATION ,  TOHOKU UNIVERSITY

    发明人： Ryusuke Nebashi ,  Noboru Sakimura ,  Yukihide Tsuji ,  Ayuka Tada ,  Tadahiko Sugibayashi ,  Takahiro Hanyu ,  Tetsuo Endoh ,  Hideo Ohno

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79 ,  H03K3/356121 ,  H03K19/18

    摘要： A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.

    摘要翻译： 非易失性逻辑门装置被配置为包括其中连接有至少三个非易失性电阻元件的存储器结构的电阻网络，作为参考电阻的参考电阻网络，其提供存储器结构对电阻网络的电阻值的容限 所述写入部分可操作以选择性地将所述电阻网络中的每个所述非易失性电阻元件的值写入或重写为对应于当数据被存储到所述电阻网络中时要读取的逻辑值的最大值或最小值， 以及可操作地作为存储器结构的逻辑值使用通过比较电阻网络的电阻值和参考电阻网络的电阻值而获得的值的逻辑电路结构。

    Nonvolatile logic gate device
    4.
    发明授权
    Nonvolatile logic gate device 有权
    非易失逻辑门装置

    公开(公告)号：US09536584B2

    公开(公告)日：2017-01-03

    申请号：US14400950

    申请日：2013-05-15

    申请人： NEC CORPORATION ,  TOHOKU UNIVERSITY

    发明人： Ryusuke Nebashi ,  Noboru Sakimura ,  Yukihide Tsuji ,  Ayuka Tada ,  Tadahiko Sugibayashi ,  Takahiro Hanyu ,  Tetsuo Endoh ,  Hideo Ohno

    IPC分类号： G11C11/00 ,  G11C11/16 ,  H03K19/18 ,  H03K3/356 ,  G11C13/00

    CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/75 ,  G11C2213/78 ,  G11C2213/79 ,  H03K3/356121 ,  H03K19/18

    摘要： A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.

    摘要翻译： 非易失性逻辑门装置被配置为包括其中连接有至少三个非易失性电阻元件的存储器结构的电阻网络，作为参考电阻的参考电阻网络，其提供存储器结构对电阻网络的电阻值的容限 所述写入部分可操作以选择性地将所述电阻网络中的每个所述非易失性电阻元件的值写入或重写为对应于当数据被存储到所述电阻网络中时要读取的逻辑值的最大值或最小值， 以及可操作地作为存储器结构的逻辑值使用通过比较电阻网络的电阻值和参考电阻网络的电阻值而获得的值的逻辑电路结构。

    MAGNETIC-DOMAIN-WALL-DISPLACEMENT MEMORY CELL AND INITIALIZING METHOD THEREFOR
    5.
    发明申请
    MAGNETIC-DOMAIN-WALL-DISPLACEMENT MEMORY CELL AND INITIALIZING METHOD THEREFOR 有权
    磁畴位移记忆细胞及其初始化方法

    公开(公告)号：US20150248939A1

    公开(公告)日：2015-09-03

    申请号：US14437197

    申请日：2013-09-13

    申请人： NEC CORPORATION ,  TOHOKU UNIVERSITY

    发明人： Ryusuke Nebashi ,  Noboru Sakimura ,  Tadahiko Sugibayashi ,  Yukihide Tsuji ,  Ayuka Tada ,  Hiroaki Honjou ,  Hideo Ohno

    IPC分类号： G11C19/08 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02

    CPC分类号： G11C19/0833 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1697 ,  G11C11/18 ,  H01L43/02 ,  H01L43/08

    摘要： Provided is a magnetic domain wall displacement memory cell, including a recording layer including a magnetic film, the recording layer including: a magnetization reversal region in which magnetization is reversible; and first and second magnetization fixed regions that supply a spin-polarized electron to the magnetization reversal region. The magnetic domain wall displacement memory cell is configured so that a first region in which magnetization reversal occurs due to a first current flowing in a direction parallel to a film surface of the recording layer and a first magnetic field component in the direction parallel to the film surface of the recording layer is formed, and a second region in which no magnetization reversal occurs is formed.

    摘要翻译： 提供一种磁畴壁位移存储单元，其包括包括磁性膜的记录层，所述记录层包括：磁化反转区域，其中磁化是可逆的; 以及向磁化反转区域提供自旋极化电子的第一和第二磁化固定区域。 磁畴壁位移存储单元被配置为使得由于在与记录层的膜表面平行的方向上流动的第一电流而产生磁化反转的第一区域和与该膜平行的方向上的第一磁场分量 形成记录层的表面，形成没有发生磁化反转的第二区域。

    Semiconductor device and programming method therefor
    6.
    发明授权
    Semiconductor device and programming method therefor 有权

    公开(公告)号：US10748614B2

    公开(公告)日：2020-08-18

    申请号：US16324782

    申请日：2017-09-11

    申请人： NEC Corporation

    发明人： Makoto Miyamura ,  Ryusuke Nebashi ,  Toshitsugu Sakamoto ,  Yukihide Tsuji ,  Xu Bai ,  Ayuka Tada

    IPC分类号： G11C13/00 ,  H03K19/17736

    摘要： In order to provide a highly reliable crossbar circuit that enables salvation of reversal of a resistive state of a variable resistance element, the semiconductor device has a configuration obtained by parallelly arranging two unit elements, each including variable-resistance two-terminal elements connected in series, the semiconductor device being provided with: a unit element group being connected to a first wiring and a second wiring; a first programming driver that changes, via the first wiring, a resistive state of the two-terminal element constituting the unit element group; a first selection transistor being connected to the first wiring and the first programming driver; a second programming driver that changes, via the second wiring, a resistive state of the two-terminal element constituting the unit element group; and a second selection transistor being connected to the second wiring and the second programming driver.

    Reconfigurable circuit
    7.
    发明授权
    Reconfigurable circuit 有权

    公开(公告)号：US10396798B2

    公开(公告)日：2019-08-27

    申请号：US15767683

    申请日：2015-10-16

    申请人： NEC Corporation

    发明人： Xu Bai ,  Toshitsugu Sakamoto ,  Munehiro Tada ,  Yukihide Tsuji ,  Ayuka Tada ,  Makoto Miyamura ,  Ryusuke Nebashi

    IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F15/78 ,  G06F17/50

    摘要： A reconfigurable circuit includes first and second wires and two or more paths active at different times. Each path includes: a first NVRS whose first terminal is connected to the first wire; a first transistor whose drain terminal is connected to a second terminal of the first NVRS; a second NVRS whose first terminal is connected to the second terminal of the first NVRS; a second transistor whose source terminal is connected to a second terminal of the second NVRS and whose drain terminal is connected to the second wire; and a 2-input AND circuit whose output is connected to a gate terminal of the first transistor. A time control signal is supplied to a first input of the 2-input AND circuit and a gate terminal of the second transistor. A write control signal is supplied to a second input of the 2-input AND circuit.

    Programmable logic integrated circuit, semiconductor device, and characterization method
    10.
    发明授权
    Programmable logic integrated circuit, semiconductor device, and characterization method 有权

    公开(公告)号：US10305485B2

    公开(公告)日：2019-05-28

    申请号：US15752330

    申请日：2016-08-31

    申请人： NEC Corporation

    发明人： Ayuka Tada ,  Noboru Sakimura ,  Makoto Miyamura ,  Yukihide Tsuji ,  Ryusuke Nebashi ,  Xu Bai ,  Toshitsugu Sakamoto

    IPC分类号： H03K19/177 ,  H01L27/24 ,  G06F17/50 ,  H01L45/00

    摘要： An object of the present invention is to provide a method for effectively performing characterization for circuit verification by static timing analysis, of a programmable logic integrated circuit including a crossbar switch including a resistance-variable element, and a logic circuit logically configured with the crossbar switch, wherein: the programmable logic integrated circuit is divided into a plurality of leaf cells including a plurality of load circuits including a part of the crossbar switch, and a power supply element input to the crossbar switch; the leaf cell is divided into delay paths each including a base leaf cell and a correction leaf cell; and circuit verification is performed based on a delay information library in which a delay time for the base leaf cell and a correction delay for the correction leaf cell are integrated into a delay time for the leaf cell.