公开(公告)号：US20170115338A1

公开(公告)日：2017-04-27

申请号：US15336687

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Sailendra Chadalavda ,  Shantanu Sarangi ,  Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Dan Smith ,  Jue Wu ,  Mahmut Yilmaz

IPC: G01R31/28

CPC classification number: G01R31/3177 ,  G01R31/2607 ,  G01R31/2803 ,  G01R31/2806 ,  G01R31/2834 ,  G01R31/31701 ,  G01R31/31707 ,  G01R31/31724 ,  G01R31/31725 ,  G01R31/318555 ,  G01R31/318572 ,  G06F11/00

Abstract: In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.

公开(公告)号：US11526644B2

公开(公告)日：2022-12-13

申请号：US17089864

申请日：2020-11-05

Applicant: Nvidia Corporation

Inventor： Kaushik Narayanun ,  Mahmut Yilmaz ,  Shantanu Sarangi ,  Jae Wu

IPC: G06F30/333 ,  G01R31/317 ,  G01R31/3185 ,  G06F30/394 ,  G06F30/323 ,  G06F115/12 ,  G06F115/02

Abstract: The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

公开(公告)号：US10281524B2

公开(公告)日：2019-05-07

申请号：US15336687

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Sailendra Chadalavda ,  Shantanu Sarangi ,  Milind Sonawane ,  Amit Sanghani ,  Jonathon E. Colburn ,  Dan Smith ,  Jue Wu ,  Mahmut Yilmaz

IPC: G01R31/3177 ,  G01R31/26 ,  G01R31/317 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/00

Abstract: In one embodiment, a test system comprises: a test partition configured to perform test operations; a centralized test controller for controlling testing by the test partition; and a test link interface controller configured to communicate between the centralized test controller and the test partition, wherein the test link interface controller controls dynamic changes to external pads associated with the test operations. The test link interface controller dynamically selects between an input direction and output direction for the external pads. The test link interface includes a pin direction controller that generates direction control signals based on the state of local test controller and communicates the desired direction to a boundary scan cell associated with the pin. The boundary scan cell programs the pad to either input or output direction depending on direction control signals. The input direction corresponds to driving test data and the output direction corresponds to observing test data.

公开(公告)号：US20230146920A1

公开(公告)日：2023-05-11

申请号：US17979246

申请日：2022-11-02

Applicant: NVIDIA CORPORATION

Inventor： Bonita Bhaskaran ,  Nithin Valentine ,  Shantanu Sarangi ,  Mahmut Yilmaz ,  Suhas Satheesh ,  Charlie Hwang ,  Tezaswi Raja ,  Kevin Zhou ,  Sailendra Chadalavada ,  Kevin Ye ,  Seyed Nima Mozaffari Mojaveri ,  Kerwin Fu

IPC: G01R31/317 ,  G01R29/26 ,  G01R31/3177

CPC classification number: G01R31/31708 ,  G01R31/31727 ,  G01R29/26 ,  G01R31/31725 ,  G01R31/3177 ,  G01R31/31905

Abstract: Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.

公开(公告)号：US10444280B2

公开(公告)日：2019-10-15

申请号：US15336676

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Dheepakkumaran Jayaraman ,  Karthikeyan Natarajan ,  Shantanu Sarangi ,  Amit Sanghani ,  Milind Sonawane ,  Sailendra Chadalavda ,  Jonathon E. Colburn ,  Kevin Wilder ,  Mahmut Yilmaz ,  Pavan Kumar Datla Jagannadha

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/26 ,  G06F11/00 ,  G01R31/317 ,  G01R31/28

Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.

公开(公告)号：US20170115352A1

公开(公告)日：2017-04-27

申请号：US15336676

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Dheepakkumaran Jayaraman ,  Karthikeyan Natarajan ,  Shantanu Sarangi ,  Amit Sanghani ,  Milind Sonawane ,  Sailendra Chadalavda ,  Jonathon E. Colburn ,  Kevin Wilder ,  Mahmut Yilmaz

IPC: G01R31/317 ,  G01R31/3177

Abstract: Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.

公开(公告)号：US20220138387A1

公开(公告)日：2022-05-05

申请号：US17089864

申请日：2020-11-05

Applicant: Nvidia Corporation

Inventor： Kaushik Narayanun ,  Mahmut Yilmaz ,  Shantanu Sarangi ,  Jae Wu

IPC: G06F30/33 ,  G06F30/323 ,  G06F30/392 ,  G06T1/20

Abstract: The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.

公开(公告)号：US10473720B2

公开(公告)日：2019-11-12

申请号：US15336626

申请日：2016-10-27

Applicant: NVIDIA CORPORATION

Inventor： Pavan Kumar Datla Jagannadha ,  Dheepakkumaran Jayaraman ,  Anubhav Sinha ,  Karthikeyan Natarajan ,  Shantanu Sarangi ,  Amit Sanghani ,  Milind Sonawane ,  Mahmut Yilmaz

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/26 ,  G01R31/28 ,  G01R31/3185 ,  G06F11/00

Abstract: In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

公开(公告)号：US12277043B2

公开(公告)日：2025-04-15

申请号：US17828162

申请日：2022-05-31

Applicant: NVIDIA Corporation

Inventor： Smbat Tonoyan ,  Mahmut Yilmaz

IPC: G06F11/263 ,  G06F11/27

Abstract: A system can include a memory and a processing device, operatively coupled to the memory, to perform operations including receiving a header block of an ordered set of blocks. The header block includes a header block payload and a first digest. The operations further include authenticating, based on the header block payload, the header block, and receiving a first data block of the ordered set of blocks. The first data block includes a first data block payload and a second digest. The operations further include authenticating, based on the first digest, the first data block, and processing the first data block payload.

公开(公告)号：US20230409452A1

公开(公告)日：2023-12-21

申请号：US17828162

申请日：2022-05-31

Applicant: NVIDIA Corporation

Inventor： Smbat Tonoyan ,  Mahmut Yilmaz

IPC: G06F11/263 ,  G06F11/27

CPC classification number: G06F11/263 ,  G06F11/27

Abstract: A system can include a memory and a processing device, operatively coupled to the memory, to perform operations including receiving a header block of an ordered set of blocks. The header block includes a header block payload and a first digest. The operations further include authenticating, based on the header block payload, the header block, and receiving a first data block of the ordered set of blocks. The first data block includes a first data block payload and a second digest. The operations further include authenticating, based on the first digest, the first data block, and processing the first data block payload.