公开(公告)号：US20190173479A1

公开(公告)日：2019-06-06

申请号：US16145741

申请日：2018-09-28

Applicant: NXP B.V.

Inventor： Vladislav Dyachenko ,  Erwin Janssen ,  Yu Lin ,  Athon Zanikopoulos

IPC: H03M1/06 ,  G01S7/35

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: a track and hold circuit (414) configured to sample an analog input signal (410); a comparator (416) coupled to the track and hold circuit and configured to compare the sampled analog input signal (410) with a DAC (444) output voltage; and a feedback path (422) that comprises a digital-to-analog converter, DAC, (444) configured to generate the reference voltage that approximates the input analog signal (410). The SAR ADC (400) further includes a dither circuit (468) coupled to or located in the feedback path (422) and arranged to add a dither signal at an input of the DAC (444) in a first time period and subtract the dither signal from the output digital signal routed via the feedback path (422) and input of the DAC (444) in a second time period during a conversion phase of the SAR ADC (400).

公开(公告)号：US10014875B1

公开(公告)日：2018-07-03

申请号：US15849856

申请日：2017-12-21

Applicant: NXP B.V.

Inventor： Athon Zanikopoulos ,  Erwin Janssen ,  Konstantinos Doris

IPC: H03M1/12 ,  H03M1/10 ,  H03M1/00 ,  H03M1/44 ,  H03M1/36 ,  H03M1/46

Abstract: An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.

公开(公告)号：US10768290B2

公开(公告)日：2020-09-08

申请号：US15835186

申请日：2017-12-07

Applicant: NXP B.V.

Inventor： Yu Lin ,  Erwin Janssen ,  Konstantinos Doris ,  Vladislav Dyachenko ,  Athon Zanikopoulos

IPC: G01S13/34 ,  G06F1/02 ,  H03D7/14 ,  H03J3/04 ,  G01R23/04

Abstract: A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state. The frequency conversion component is arranged to derive the frequency estimation signal from the continuous waveform signal output by the continuous waveform generator component.

公开(公告)号：US20180191365A1

公开(公告)日：2018-07-05

申请号：US15849856

申请日：2017-12-21

Applicant: NXP B.V.

Inventor： Athon Zanikopoulos ,  Erwin Janssen ,  Konstantinos Doris

IPC: H03M1/10 ,  H03M1/00 ,  H03M1/12 ,  H03M1/44

CPC classification number: H03M1/1009 ,  H03M1/001 ,  H03M1/002 ,  H03M1/1028 ,  H03M1/1057 ,  H03M1/1071 ,  H03M1/1076 ,  H03M1/1245 ,  H03M1/361 ,  H03M1/44 ,  H03M1/46 ,  H03M1/468

Abstract: An analog-to-digital converter including a converter arrangement configured to provide a digital output signal as an output of the analog-to-digital converter based on an analog input signal comprising an input to the analog-to-digital converter, the analog-to-digital converter including a calibration module configured to provide calibration signalling to set one or more of a gain of one or more components of the converter arrangement and an offset of one or more components of the converter arrangement, the calibration module further configured to provide, as an output, diagnostic information based on the calibration signalling for use in determining the occurrence of a fault in the analog-to-digital converter.