公开(公告)号：US20130273731A1

公开(公告)日：2013-10-17

申请号：US13916430

申请日：2013-06-12

Applicant: NXP B.V.

Inventor： Jan GULPEN ,  Tonny KAMPHUIS ,  Pieter HOCHSTENBACH ,  Leo VAN GEMERT ,  Eric Van GRUNSVEN ,  Marc De SAMBER

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.

Abstract translation: 芯片级封装具有半导体管芯，其具有以每单位面积的焊盘密度排列的管芯接合焊盘的阵列，嵌入在具有支撑导电触头阵列的表面的模制模具支撑体中，每个触点通过电连接 导致相应的一个管芯接合焊盘。

公开(公告)号：US20190011496A1

公开(公告)日：2019-01-10

申请号：US16030006

申请日：2018-07-09

Applicant: NXP B.V.

Inventor： Leo VAN GEMERT ,  Peter DRUMMEN

IPC: G01R31/28 ,  H01L23/58 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L21/78

Abstract: An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.

公开(公告)号：US20180233465A1

公开(公告)日：2018-08-16

申请号：US15871440

申请日：2018-01-15

Applicant: NXP B.V.

Inventor： Maristella SPELLA ,  Waqas Hassan SYED ,  Daniele CAVALLO ,  Mingda HUANG ,  Leo VAN GEMERT

IPC: H01L23/66 ,  H01Q19/10 ,  H01L23/528 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/528 ,  H01L24/16 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1423 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/30105 ,  H01Q1/2283 ,  H01Q1/40 ,  H01Q13/16 ,  H01Q15/10 ,  H01Q19/09 ,  H01Q19/10 ,  H01Q19/28 ,  H01Q21/064

Abstract: An integrated circuit package is described comprising an integrated circuit die and an antenna structure coupled to the integrated circuit die and comprising a stacked arrangement of metal and dielectric layers, wherein a first metal layer includes a planar antenna and at least one further metal layer comprises an artificial dielectric layer. The integrated circuit package may improve the directionality of the antenna and reduces the sensitivity of the antenna to the printed circuit board on which the integrated circuit package is mounted.