公开(公告)号：US20130273731A1

公开(公告)日：2013-10-17

申请号：US13916430

申请日：2013-06-12

申请人： NXP B.V.

发明人： Jan GULPEN ,  Tonny KAMPHUIS ,  Pieter HOCHSTENBACH ,  Leo VAN GEMERT ,  Eric Van GRUNSVEN ,  Marc De SAMBER

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92144 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

摘要： A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads.

摘要翻译： 芯片级封装具有半导体管芯，其具有以每单位面积的焊盘密度排列的管芯接合焊盘的阵列，嵌入在具有支撑导电触头阵列的表面的模制模具支撑体中，每个触点通过电连接 导致相应的一个管芯接合焊盘。

公开(公告)号：US20140091458A1

公开(公告)日：2014-04-03

申请号：US14021708

申请日：2013-09-09

申请人： NXP B.V.

发明人： Leonardus Antonius Elisabeth VAN GEMERT ,  Tonny KAMPHUIS ,  Hartmut BUENNING ,  Christian ZENZ

IPC分类号： H01L23/28 ,  H01L21/78

CPC分类号： H01L23/28 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/96 ,  H01L24/97 ,  H01L41/338 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/00

摘要： Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.

摘要翻译： 与示例性实施例一致，存在组装以抵抗机械损坏的半导体器件。 半导体器件包括限定在顶表面上的有源电路，提供与有源电路的电连接的接触区域。 有一个基座结构，有源电路安装在基座结构的相对的底面上; 基座结构的面积小于有源器件的面积。 由模制化合物组成的封装围绕有源器件的侧面和下侧并且围绕接触区域。 封装提供了弹性表面，保护有源器件免受机械损坏。 该实施例的特征在于，接触区域可以具有限定在其上的焊料凸块。

公开(公告)号：US20150162306A1

公开(公告)日：2015-06-11

申请号：US14626832

申请日：2015-02-19

申请人： NXP B.V.

发明人： Leonardus Antonius Elisabeth VAN GEMERT ,  Tonny KAMPHUIS ,  Hartmut BUENNING ,  Christian ZENZ

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

CPC分类号： H01L23/28 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/96 ,  H01L24/97 ,  H01L41/338 ,  H01L2224/12105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/181 ,  H01L2924/00

摘要： Consistent with an example embodiment, there is semiconductor device assembled to resist mechanical damage. The semiconductor device comprises an active circuit defined on a top surface, contact areas providing electrical connection to the active circuit. There is a pedestal structure upon which the active circuit is mounted on an opposite bottom surface; the pedestal structure has an area smaller than the area of the active device. An encapsulation, consisting of a molding compound, surrounds the sides and the underside of the active device and it surrounds the contact areas. The encapsulation provides a resilient surface protecting the active device from mechanical damage. A feature of the embodiment is that the contact areas may have solder bumps defined thereon.

摘要翻译： 与示例性实施例一致，存在组装以抵抗机械损坏的半导体器件。 半导体器件包括限定在顶表面上的有源电路，提供与有源电路的电连接的接触区域。 有一个基座结构，有源电路安装在基座结构的相对的底面上; 基座结构的面积小于有源器件的面积。 由模制化合物组成的封装围绕有源器件的侧面和下侧并且围绕接触区域。 封装提供了弹性表面，保护有源器件免受机械损坏。 该实施例的特征在于，接触区域可以具有限定在其上的焊料凸块。

公开(公告)号：US20140138855A1

公开(公告)日：2014-05-22

申请号：US13967164

申请日：2013-08-14

申请人： NXP B.V.

发明人： Leonardus Antonius Elisabeth VAN GEMERT ,  Hartmut BUENNING ,  Tonny KAMPHUIS ,  Sascha MOELLER ,  Christian ZENZ

IPC分类号： H01L21/782 ,  H01L23/00

CPC分类号： H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

摘要： Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die. Each individual device die has a protective layer on the back-side, the protective layer having a stand-off distance from a vertical edge of the individual device die.

摘要翻译： 与示例性实施例一致，存在用于组装晶片级芯片尺寸处理（WLCSP）晶片的方法; 晶片具有顶侧表面和背面表面，以及在顶侧表面上具有电触头的多个器件裸片。 该方法包括对晶片的背面进行背面研磨至厚度。 在晶片的背面上模制厚度保护层。 将晶片安装在锯片上; 沿着多个器件裸片的锯条，晶片被锯切，锯切发生在第一切口的刀片和背面晶片厚度的深度上。 再次，晶片沿着多个器件裸片的锯条被锯切，锯切发生在第二切口的刀片上，第二切口比第一切口窄，并锯切到保护层厚度的深度。 将多个器件裸片分离为单个器件管芯。 每个单独的器件管芯在背面具有保护层，保护层具有与单独器件管芯的垂直边缘的间隔距离。

公开(公告)号：US20140110842A1

公开(公告)日：2014-04-24

申请号：US13967084

申请日：2013-08-14

申请人： NXP B.V.

发明人： Christian ZENZ ,  Hartmut BUENNING ,  Leonardus Antonius Elisabeth VAN GEMERT ,  Tonny KAMPHUIS ,  Sascha MOELLER

IPC分类号： H01L21/782 ,  H01L23/498

CPC分类号： H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

摘要： Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (θ) of tooling impact upon a vertical face the semiconductor device.

摘要翻译： 与示例性实施例一致，存在半导体器件，其中有源器件具有正面和背面; 总体厚度的半导体器件包括具有限定在前侧表面上的电路的有源器件，前侧表面具有区域。 有源器件的背面具有有源器件厚度的部分深度和大约部分深度的宽度的凹部，在垂直边缘处围绕有源器件的凹部。 在有源器件的背面具有厚度的保护层，该保护材料的面积大于第一区域并具有间隔距离。 垂直边缘具有填充与垂直边缘齐平的凹部的保护层。 保护材料的间隔距离是半导体器件厚度和在半导体器件的垂直面上的工具冲击的角度（＆amp;）的切线的函数。