公开(公告)号：US20200065647A1

公开(公告)日：2020-02-27

申请号：US16550515

申请日：2019-08-26

申请人： NaMLab gGmbH

发明人： Halid Mulaosmanovic ,  Stefan Slesazeck

IPC分类号： G06N3/04 ,  G06N3/06 ,  G11C11/54 ,  G11C11/22 ,  H01L27/11502

摘要： An artificial neuron integrated circuit including a polarizable circuit element having a first electrode, a second electrode, and a polarizable material layer disposed between the first and second electrodes, the polarizable material layer changeable between a first polarization state and a second polarization state, in response to receiving a number of voltage pulses across the first and second electrodes, the polarizable material layer to change from one of the first and second polarization states to the other of the first and second polarization states, where each of the number of voltage pulses individually is insufficient to change the polarization state.

公开(公告)号：US10963776B2

公开(公告)日：2021-03-30

申请号：US16550515

申请日：2019-08-26

申请人： NaMLab gGmbH

发明人： Halid Mulaosmanovic ,  Stefan Slesazeck

IPC分类号： G11C11/22 ,  G06N3/04 ,  G06N3/06 ,  H01L27/11502 ,  G11C11/54

摘要： An artificial neuron integrated circuit including a polarizable circuit element having a first electrode, a second electrode, and a polarizable material layer disposed between the first and second electrodes, the polarizable material layer changeable between a first polarization state and a second polarization state, in response to receiving a number of voltage pulses across the first and second electrodes, the polarizable material layer to change from one of the first and second polarization states to the other of the first and second polarization states, where each of the number of voltage pulses individually is insufficient to change the polarization state.

公开(公告)号：US20190172539A1

公开(公告)日：2019-06-06

申请号：US15829076

申请日：2017-12-01

申请人： NaMLab gGmbH

发明人： Stefan Slesazeck ,  Halid Mulaosmanovic ,  Evelyn Breyer

IPC分类号： G11C14/00 ,  G11C13/00 ,  H01L21/28 ,  H01L27/10 ,  H01L27/11507

CPC分类号： G11C14/0072 ,  G11C7/1006 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/5657 ,  G11C13/0004 ,  G11C14/009 ,  H01L27/101 ,  H01L27/11507 ,  H01L29/40111 ,  H03K19/0944

摘要： A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.

公开(公告)号：US10424379B2

公开(公告)日：2019-09-24

申请号：US15829076

申请日：2017-12-01

申请人： NaMLab gGmbH

发明人： Stefan Slesazeck ,  Halid Mulaosmanovic ,  Evelyn Breyer

IPC分类号： G11C11/22 ,  H03K19/0944 ,  G11C14/00 ,  H01L27/11507 ,  H01L21/28 ,  H01L27/10 ,  G11C13/00

摘要： A polarization-based logic gate includes a transistor having a drain and a polarizable material layer having at least two polarization states, the polarization state representing a first logic value, and a resistive element having a first terminal coupled to the drain and a second terminal. A plurality of input/output terminals connected to the transistor and second terminal of the resistive element so as to apply voltages to selected input/output terminals, including a sensing voltage representing a second logic value, with a resulting drain current of the transistor at least partially flowing through the resistive element and representing a result of a logic operation between the first logic value and the second logic value.

公开(公告)号：US10043567B2

公开(公告)日：2018-08-07

申请号：US15823230

申请日：2017-11-27

申请人： NaMLab gGmbH

发明人： Stefan Slesazeck ,  Halid Mulaosmanovic

IPC分类号： G11C11/00 ,  G11C11/22 ,  H01L29/78 ,  H01L29/51 ,  H01L27/11507 ,  H01L49/02 ,  H01L27/1159

摘要： An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.

公开(公告)号：US09830969B2

公开(公告)日：2017-11-28

申请号：US15367629

申请日：2016-12-02

申请人： NaMLab gGmbH

发明人： Stefan Slesazeck ,  Halid Mulaosmanovic

IPC分类号： G11C11/22 ,  H01L27/11507 ,  H01L27/1159 ,  H01L49/02 ,  H01L29/51 ,  H01L29/78

CPC分类号： G11C11/2275 ,  G11C11/221 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/5657 ,  H01L27/11507 ,  H01L27/1159 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0676 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

摘要： An integrated circuit includes a ferroelectric memory cell. The ferroelectric memory cell includes a ferroelectric layer stack comprising at least one ferroelectric material oxide layer. Each of the ferroelectric material oxide layers includes a ferroelectric material that is at least partially in a ferroelectric state. The ferroelectric layer stack comprises at least two ferroelectric domains. Further, the voltage which is to applied to the layer stack to induce polarization reversal differs for the individual domains such that polarization reversal of individual domains or of a portion of the totality of ferroelectric domains within the ferroelectric material of can be attained.