Interference-aware assignment of programming levels in analog memory cells
    1.
    发明授权
    Interference-aware assignment of programming levels in analog memory cells 有权
    模拟存储器单元中编程级别的干扰感知分配

    公开(公告)号:US08595591B1

    公开(公告)日:2013-11-26

    申请号:US13176761

    申请日:2011-07-06

    摘要: A method for data storage includes accepting data for storage in a memory including multiple analog memory cells. For each memory cell, a respective set of nominal analog values is assigned for representing data values to be stored in the memory cell, by choosing the nominal analog values for a given memory cell in a respective range that depends on interference between the given memory cell and at least one other memory cell in the memory. The data is stored in each memory cell using the respective selected set of the nominal analog values.

    摘要翻译: 一种用于数据存储的方法包括接收用于存储在包括多个模拟存储器单元的存储器中的数据。 对于每个存储器单元,通过在取决于给定存储器单元之间的干扰的相应范围内选择给定存储器单元的额定模拟值,分配相应的一组标称模拟值来表示要存储在存储单元中的数据值 以及存储器中的至少一个其它存储单元。 使用相应选定的标称模拟值集合将数据存储在每个存储单元中。

    Programming Schemes for Multi-Level Analog Memory Cells
    5.
    发明申请
    Programming Schemes for Multi-Level Analog Memory Cells 有权
    多级模拟存储单元的编程方案

    公开(公告)号:US20120297270A1

    公开(公告)日:2012-11-22

    申请号:US13566372

    申请日:2012-08-03

    IPC分类号: G11C16/10 G06F11/10 H03M13/05

    摘要: A method for data storage includes storing first data bits in a set of multi-bit analog memory cells at a first time by programming the memory cells to assume respective first programming levels. Second data bits are stored in the set of memory cells at a second time that is later than the first time by programming the memory cells to assume respective second programming levels that depend on the first programming levels and on the second data bits. A storage strategy is selected responsively to a difference between the first and second times. The storage strategy is applied to at least one group of the data bits, selected from among the first data bits and the second data bits.

    摘要翻译: 一种用于数据存储的方法包括:通过对存储器单元进行编程来采用各自的第一编程级别,来将第一数据位在第一时间存储在一组多位模拟存储单元中。 第二数据位通过对存储器单元进行编程以采取依赖于第一编程电平和第二数据位的相应的第二编程电平而在比第一时间晚的第二时间存储在存储单元组中。 响应于第一次和第二次之间的差异选择存储策略。 将存储策略应用于从第一数据位和第二数据位中选择的至少一组数据位。

    Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
    6.
    发明授权
    Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N 有权
    在N位/单元模拟存储单元器件中以M位/单元密度存储,M> N

    公开(公告)号:US08208304B2

    公开(公告)日:2012-06-26

    申请号:US12618732

    申请日:2009-11-15

    IPC分类号: G11C16/04

    摘要: A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells and supports a set of built-in programming commands. Each of the programming commands programs a respective page, selected from a group of N pages, in a subset of the memory cells. The subset of the memory cells is programmed to store M pages of the data, M>N, by performing a sequence of the programming commands drawn only from the set.

    摘要翻译: 一种用于数据存储的方法包括接收用于存储在包括多个模拟存储器单元的存储器中的数据,并且支持一组内置的编程命令。 每个编程命令在存储器单元的子集中编写从一组N页中选择的相应页面。 存储器单元的子集被编程为通过执行仅从集合中绘制的编程命令的序列来存储数据的M页M> N。

    DISTORTION ESTIMATION AND CANCELLATION IN MEMORY DEVICES
    7.
    发明申请
    DISTORTION ESTIMATION AND CANCELLATION IN MEMORY DEVICES 有权
    存储器件中的失真估计和消除

    公开(公告)号:US20120026789A1

    公开(公告)日:2012-02-02

    申请号:US13239411

    申请日:2011-09-22

    IPC分类号: G11C16/06

    摘要: A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.

    摘要翻译: 用于操作存储器(28)的方法包括将存储器的一组模拟存储器单元(32)中的数据存储为相应的第一电压电平。 在存储数据之后,从相应的模拟存储器单元读取第二电压电平。 第二电压电平受到交叉耦合干扰的影响,导致第二电压电平与相应的第一电压电平不同。 通过处理第二电压电平来估计量化模拟存储器单元之间的交叉耦合干扰的交叉耦合系数。 使用估计的交叉耦合系数,从读取的第二电压电平重建存储在模拟存储器单元组中的数据。

    Reading memory cells using multiple thresholds
    8.
    发明授权
    Reading memory cells using multiple thresholds 有权
    使用多个阈值读取存储单元

    公开(公告)号:US07975192B2

    公开(公告)日:2011-07-05

    申请号:US11995814

    申请日:2007-10-30

    IPC分类号: G11C29/42 G11C29/50

    摘要: A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog memory cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. At least two of the read thresholds are positioned between a pair of the nominal values that are adjacent to one another in the set of the nominal values. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.

    摘要翻译: 一种用于操作存储器(28)的方法包括:通过将从一组标称值中选择的相应模拟输入值写入到存储器的模拟存储器单元(32)中来存储用错误校正码(ECC)编码的数据, 模拟存储单元。 通过执行将模拟存储器单元的模拟输出值与不同的相应读取阈值进行比较的多个读取操作来读取存储的数据,以便为每个模拟存储器单元产生多个比较结果。 读取阈值中的至少两个位于在标称值的集合中彼此相邻的一对标称值之间。 响应于多个比较结果计算软指标。 使用软指标对ECC进行解码,以便提取存储在模拟存储单元中的数据。

    Memory cell readout using successive approximation
    9.
    发明授权
    Memory cell readout using successive approximation 有权
    使用逐次逼近的存储单元读数

    公开(公告)号:US07821826B2

    公开(公告)日:2010-10-26

    申请号:US11995805

    申请日:2007-10-30

    IPC分类号: G11C16/04

    摘要: A method for operating a memory (20) includes storing analog values in an array of analog memory cells (22), so that each of the analog memory cells holds an analog value corresponding to at least first and second respective bits. A first indication of the analog value stored in a given analog memory cell is obtained using a first set of sampling parameters. A second indication of the analog value stored in the given analog memory cell is obtained using a second set of sampling parameters, which is dependent upon the first indication. The first and second respective bits are read out from the given analog memory cell responsively to the first and second indications.

    摘要翻译: 一种用于操作存储器(20)的方法包括将模拟值存储在模拟存储器单元(22)的阵列中,使得每个模拟存储器单元保持与至少第一和第二相应位对应的模拟值。 使用第一组采样参数获得存储在给定模拟存储器单元中的模拟值的第一指示。 使用取决于第一指示的第二组采样参数来获得存储在给定模拟存储器单元中的模拟值的第二指示。 响应于第一和第二指示,从给定的模拟存储单元读出第一和第二各自的位。

    DATA STORAGE WITH INCREMENTAL REDUNDANCY
    10.
    发明申请
    DATA STORAGE WITH INCREMENTAL REDUNDANCY 有权
    数据存储与增量冗余

    公开(公告)号:US20080282106A1

    公开(公告)日:2008-11-13

    申请号:US12119069

    申请日:2008-05-12

    IPC分类号: G06F11/16

    CPC分类号: G06F11/1068 G11C2029/0411

    摘要: A method for operating a memory includes encoding input data with an Error Correction Code (ECC) to produce input encoded data including first and second sections, such that the ECC is decodable based on the first section at a first redundancy, and based on both the first and the second sections at a second redundancy that is higher than the first redundancy.Output encoded data is read and a condition is evaluated. The input data is reconstructed using a decoding level selected, responsively to the condition, from a first level, at which a first part of the output encoded data corresponding to the first section is processed to decode the ECC at the first redundancy, and a second level, at which the first part and a second part of the output encoded data corresponding to the second section are processed jointly to decode the ECC at the second redundancy.

    摘要翻译: 一种用于操作存储器的方法包括用错误校正码(ECC)编码输入数据以产生包括第一和第二部分的输入编码数据,使得基于第一冗余部分的第一部分可以解码ECC,并且基于两者 第一和第二部分具有高于第一冗余的第二冗余。 读取输出编码数据并评估条件。 输入数据使用从第一级别选择的解码级别来重构,在第一级别处理对应于第一部分的输出编码数据的第一部分被处理以在第一冗余处解码ECC,以及第二级 级别,其中对应于第二部分的输出编码数据的第一部分和第二部分共同处理,以在第二冗余处对ECC进行解码。