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    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE 有权

    公开(公告)号：US20090154213A1

    公开(公告)日：2009-06-18

    申请号：US12347233

    申请日：2008-12-31

    申请人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    发明人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    IPC分类号： G11C5/02 ,  G11C8/00 ,  G11C7/06 ,  G11C5/06

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US20090154265A1

    公开(公告)日：2009-06-18

    申请号：US12347239

    申请日：2008-12-31

    申请人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    发明人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    IPC分类号： G11C11/416 ,  G11C8/00

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。

    METHOD OF FABRICATING METAL-INSULATOR-METAL CAPACITOR
    4.
    发明申请
    METHOD OF FABRICATING METAL-INSULATOR-METAL CAPACITOR 审中-公开
    金属绝缘体 - 金属电容器的制造方法

    公开(公告)号：US20070026625A1

    公开(公告)日：2007-02-01

    申请号：US11460916

    申请日：2006-07-28

    申请人： Jung-Hee CHUNG ,  Jong-Cheol LEE ,  Jae-Hyoung CHOI ,  Jeong-Sik CHOI ,  Se-Hoon OH ,  Cha-Young YOO

    发明人： Jung-Hee CHUNG ,  Jong-Cheol LEE ,  Jae-Hyoung CHOI ,  Jeong-Sik CHOI ,  Se-Hoon OH ,  Cha-Young YOO

    IPC分类号： H01L21/473

    CPC分类号： H01L21/02181 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3142 ,  H01L21/3162 ,  H01L21/31645 ,  H01L28/91

    摘要： In one embodiment, a method of fabricating a MIM capacitor includes forming an interlayer insulating layer having a contact plug on a semiconductor substrate, forming an etch stop layer on the interlayer insulating layer, and forming a mold layer having an opening exposing the contact plug on the etch stop layer. Next, a first conductive layer for the lower electrode is formed on the sidewalls and the bottom of the opening, and a photoresistive layer is formed on the first conductive layer. The mold layer and the photoresistive layer are then removed, and a composite dielectric layer is formed on the lower electrode. A second conductive layer is then formed on the composite dielectric layer. The composite dielectric layer may be composed of an oxide hafnium (HfO2) dielectric layer and an oxide aluminum (Al2O3) dielectric layer, with the oxide hafnium dielectric layer having a thickness of about 20 Å to about 50 Å. The oxide aluminum dielectric layer is formed with a thickness determined by subtracting the thickness of the oxide hafnium dielectric layer from a composite dielectric layer thickness corresponding to an equivalent oxide dielectric layer thickness set to provide a predetermined capacitance of the capacitor.

    摘要翻译： 在一个实施例中，制造MIM电容器的方法包括在半导体衬底上形成具有接触插塞的层间绝缘层，在层间绝缘层上形成蚀刻停止层，并形成具有露出接触插头的开口的模具层 蚀刻停止层。 接下来，在开口的侧壁和底部形成用于下电极的第一导电层，并且在第一导电层上形成光刻胶层。 然后去除模具层和光致抗蚀剂层，并且在下部电极上形成复合电介质层。 然后在复合电介质层上形成第二导电层。 复合电介质层可以由氧化铪（HfO 2/2）介电层和氧化铝（Al 2 O 3 3）介电层 氧化铪介电层的厚度约为20至50埃。 形成氧化铝介电层，其厚度通过从设置为提供电容器的预定电容的等效氧化物介电层厚度对应的复合电介质层厚度减去氧化铪电介质层的厚度而确定。