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    Semiconductor memory device with hierarchical bit line structure
    1.
    发明申请
    Semiconductor memory device with hierarchical bit line structure 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US20070115710A1

    公开(公告)日：2007-05-24

    申请号：US11480447

    申请日：2006-07-05

    申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C5/06

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

    Semiconductor memory device with hierarchical bit line structure
    2.
    发明授权
    Semiconductor memory device with hierarchical bit line structure 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US07656723B2

    公开(公告)日：2010-02-02

    申请号：US12347239

    申请日：2008-12-31

    申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C7/22

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

    Semiconductor memory device with hierarchical bit line structure
    3.
    发明授权
    Semiconductor memory device with hierarchical bit line structure 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US07489570B2

    公开(公告)日：2009-02-10

    申请号：US11480447

    申请日：2006-07-05

    申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C7/00

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。

    Semiconductor memory device with hierarchical bit line structure
    4.
    发明授权
    Semiconductor memory device with hierarchical bit line structure 有权

    公开(公告)号：US07616512B2

    公开(公告)日：2009-11-10

    申请号：US12347233

    申请日：2008-12-31

    申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C7/00

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    Data line layout and line driving method in semiconductor memory device
    5.
    发明申请
    Data line layout and line driving method in semiconductor memory device 有权
    半导体存储器件中的数据线布局和线驱动方法

    公开(公告)号：US20080165559A1

    公开(公告)日：2008-07-10

    申请号：US12006502

    申请日：2008-01-03

    申请人： Nam-Seog Kim ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C5/06 ,  G11C7/10

    CPC分类号： G11C5/063 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18 ,  G11C11/417

    摘要： A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.

    摘要翻译： 数据线布局结构包括多个第一数据线，第二数据线，第三数据线，第一数据线驱动器和第二数据线驱动器。 多个第一数据线连接到存储器垫中的子垫，使得预定数量的第一数据线连接到每个子垫。 第二数据线的布置量比第一数据线的数量少，从而形成相对于第一数据线的层次。 第三数据线被布置成相对于第二数据线形成层级，并且将通过第二数据线提供的数据传送到数据锁存器。 第一数据线驱动器连接在第一数据线和第二数据线之间，并且执行用于输出第一数据线的逻辑“或”运算，以驱动对应的第二数据线。 第二数据线驱动器连接在第二数据线和第三数据线之间，并且执行用于输出第二数据线的逻辑“或”运算，以驱动第三数据线。

    Data line layout and line driving method in semiconductor memory device
    6.
    发明授权
    Data line layout and line driving method in semiconductor memory device 有权
    半导体存储器件中的数据线布局和线驱动方法

    公开(公告)号：US07697314B2

    公开(公告)日：2010-04-13

    申请号：US12006502

    申请日：2008-01-03

    申请人： Nam-Seog Kim ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18 ,  G11C11/417

    摘要： A data line layout structure comprises a plurality of first data lines, second data lines, a third data line, a first data line driver, and a second data line driver. The plurality of first data lines are connected to sub mats in a memory mat so that a predetermined number of first data lines are connected to each sub mat. The second data lines are disposed in a smaller quantity than the number of the first data lines so as to form a hierarchy with respect to the first data lines. The third data line is disposed to form a hierarchy with respect to the second data lines, and transfers data provided through the second data lines to a data latch. The first data line driver is connected between the first data lines and the second data lines, and performs a logical ORing operation for output of the first data lines so as to drive a corresponding second data line. The second data line driver is connected between the second data lines and the third data line, and performs a logical ORing operation for output of the second data lines so as to drive the third data line.

    摘要翻译： 数据线布局结构包括多个第一数据线，第二数据线，第三数据线，第一数据线驱动器和第二数据线驱动器。 多个第一数据线连接到存储器垫中的子垫，使得预定数量的第一数据线连接到每个子垫。 第二数据线的布置量比第一数据线的数量少，从而形成相对于第一数据线的层次。 第三数据线被布置成相对于第二数据线形成层级，并且将通过第二数据线提供的数据传送到数据锁存器。 第一数据线驱动器连接在第一数据线和第二数据线之间，并且执行用于输出第一数据线的逻辑“或”运算，以驱动对应的第二数据线。 第二数据线驱动器连接在第二数据线和第三数据线之间，并且执行用于输出第二数据线的逻辑“或”运算，以驱动第三数据线。

    AMPLIFIER CIRCUIT HAVING CONSTANT OUTPUT SWING RANGE AND STABLE DELAY TIME
    7.
    发明申请
    AMPLIFIER CIRCUIT HAVING CONSTANT OUTPUT SWING RANGE AND STABLE DELAY TIME 失效
    具有恒定输出振荡范围和稳定延迟时间的放大器电路

    公开(公告)号：US20070139084A1

    公开(公告)日：2007-06-21

    申请号：US11627794

    申请日：2007-01-26

    申请人： Nam-Seog KIM ,  Yong-Jin Yoon ,  Uk-Rae Cho

    发明人： Nam-Seog KIM ,  Yong-Jin Yoon ,  Uk-Rae Cho

    IPC分类号： H03K5/22

    CPC分类号： H03K3/356139

    摘要： Provided is an amplifier circuit having a constant output swing range and a stable delay time, where the amplifier circuit includes a first bias unit, a second bias unit, a comparison unit, and an amplifier unit, and the first bias unit responds to an internal reference signal with a predetermined voltage level and maintains constant the amount of a first current, and the second bias unit receives an external reference signal, responds to a control voltage, and controls the amount of a second current to be the same as the amount of the first current, and the comparison unit compares a voltage level of a first node with a voltage level of a second node, and controls a voltage level of the control voltage according to the comparison result, and the amplifier unit compares a voltage level of an external input signal with a voltage level of the external reference signal, amplifies and outputs a voltage difference between the two compared signals, responds to the control voltage, and controls the amount of a third current to be the same as the amount of the first current although the level of the external reference signal is varied, such that the amplifier circuit and a circuit for receiving data can maintain a constant output swing range and a stable delay time irrespective of variations in the voltage levels of the external input signal or the external reference signal.

    摘要翻译： 提供了具有恒定的输出摆幅范围和稳定延迟时间的放大器电路，其中放大器电路包括第一偏置单元，第二偏置单元，比较单元和放大器单元，并且第一偏置单元响应内部 具有预定电压电平的参考信号并且保持第一电流的量的恒定，并且第二偏置单元接收外部参考信号，响应于控制电压，并且将第二电流的量控制为与第 第一电流和比较单元将第一节点的电压电平与第二节点的电压电平进行比较，并且根据比较结果控制控制电压的电压电平，并且放大器单元将电压电平 具有外部参考信号电压电平的外部输入信号，放大并输出两个比较信号之间的电压差，响应控制电压，并控制 尽管外部参考信号的电平变化，但是第三电流的量与第一电流的量相同，使得放大器电路和用于接收数据的电路可以保持恒定的输出摆幅范围和稳定的 延迟时间，而不管外部输入信号或外部参考信号的电压电平的变化。

    Integrated circuit with on-chip termination
    9.
    发明授权
    Integrated circuit with on-chip termination 有权
    具有片上终端的集成电路

    公开(公告)号：US06930508B2

    公开(公告)日：2005-08-16

    申请号：US10626015

    申请日：2003-07-24

    申请人： Nam-Seog Kim ,  Uk-Rae Cho ,  Tae-Hyoung Kim

    发明人： Nam-Seog Kim ,  Uk-Rae Cho ,  Tae-Hyoung Kim

    IPC分类号： H03H11/40 ,  H03B1/00 ,  H03K19/003 ,  H04L25/02

    CPC分类号： H04L25/0278

    摘要： There is provided an integrated circuit which performs data input/output operations through a transmission line with a predetermined impedance. The integrated circuit includes a driver having a plurality of driving units, in which the driving units input/output data from/to the transmission line, and a controller for inputting an output data signal and applying a plurality of control signals to the driver, in which the control signals are generated in response to an output activation signal and impedance code signals related to states of the impedance. At least one driving unit is driven in response to the control signals, and the driver includes an on-chip termination circuit connected to an input buffer.

    摘要翻译： 提供了通过具有预定阻抗的传输线执行数据输入/输出操作的集成电路。 集成电路包括具有多个驱动单元的驱动器，其中驱动单元从/向传输线输入/输出数据，以及用于输入输出数据信号并将多个控制信号施加到驾驶员的控制器， 其响应于与阻抗状态相关的输出激活信号和阻抗代码信号而产生控制信号。 响应于控制信号驱动至少一个驱动单元，并且驱动器包括连接到输入缓冲器的片上终端电路。

    Apparatus for generating internal clock signal
    10.
    发明申请
    Apparatus for generating internal clock signal 失效
    用于产生内部时钟信号的装置

    公开(公告)号：US20050146365A1

    公开(公告)日：2005-07-07

    申请号：US11031129

    申请日：2005-01-07

    申请人： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Yong-Jin Yoon ,  Uk-Rae Cho

    IPC分类号： G11C11/40 ,  G11C7/00 ,  G11C8/00 ,  G11C11/407 ,  H03K5/13 ,  H03K5/135 ,  H03L7/06 ,  H03L7/081

    CPC分类号： H03L7/0812 ,  H03K5/133 ,  H03K5/135

    摘要： An apparatus for generating an internal clock signal for acquisition of accurate synchronization is provided. The apparatus including: an input buffer for buffering the external clock signal to output a first reference clock signal; a delay compensation circuit for delaying the first reference clock signal; a forward delay array; a mirror control circuit comprising a plurality of phase detectors for detecting delayed clock signals synchronized with a second reference clock signal; a backward delay array; and an output buffer to generate an internal clock signal. An internal clock signal in accurate synchronization with the reference clock signal can be generated by minimizing the delay and distortion of the reference clock signal.

    摘要翻译： 提供一种用于产生用于获取精确同步的内部时钟信号的装置。 该装置包括：输入缓冲器，用于缓冲外部时钟信号以输出第一参考时钟信号; 延迟补偿电路，用于延迟第一参考时钟信号; 前向延迟阵列 镜控制电路，包括用于检测与第二参考时钟信号同步的延迟时钟信号的多个相位检测器; 后向延迟阵列 以及产生内部时钟信号的输出缓冲器。 可以通过最小化参考时钟信号的延迟和失真来产生与参考时钟信号精确同步的内部时钟信号。