公开(公告)号：US5214296A

公开(公告)日：1993-05-25

申请号：US848840

申请日：1992-03-10

申请人： Yoshiro Nakata ,  Naoto Matsuo ,  Toshiki Yabu ,  Susumu Matsumoto ,  Shozo Okada

发明人： Yoshiro Nakata ,  Naoto Matsuo ,  Toshiki Yabu ,  Susumu Matsumoto ,  Shozo Okada

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78642 ,  H01L27/10817

摘要： A thin-film semiconductor device having a vertical TFT which includes a gate insulating film formed on a sidewall of a throughhole formed in an insulating layer; a thin-film semiconductor layer formed on the gate insulating film; and a gate electrode formed within the insulating layer. The gate electrode, the gate insulating film, and the thin-film semiconductor layer together form a lateral MOS structure. The thin-film semiconductor layer is connected to a bit line at the bottom of the throughhole and to a storage node of a capacitor formed over the switching transistor.

摘要翻译： 一种具有垂直TFT的薄膜半导体器件，其包括形成在绝缘层中形成的通孔的侧壁上的栅极绝缘膜; 形成在所述栅极绝缘膜上的薄膜半导体层; 以及形成在所述绝缘层内的栅电极。 栅电极，栅极绝缘膜和薄膜半导体层一起形成横向MOS结构。 薄膜半导体层连接到通孔底部的位线和形成在开关晶体管上的电容器的存储节点。

公开(公告)号：US5399890A

公开(公告)日：1995-03-21

申请号：US257955

申请日：1994-06-10

申请人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

发明人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L27/105 ,  H01L27/10808

摘要： A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.

摘要翻译： 本发明的半导体存储器包括具有多个晶体管的半导体衬底，与多个晶体管的一部分连接的多个叠层电容器，与多个晶体管的其它部分连接的多个第一级互连层，以及多个晶体管的多个 位于层叠电容器和第一级互连层之上的第二级互连层。 多个叠层电容器中的每一个包括第一电极层，形成在第一电极层顶部的电容绝缘膜，以及形成在电容绝缘膜顶部的第二电极层。 第二电极层连接到多个第二级互连层之一的一部分。 多个第一级互连层的至少一部分连接到多个第二级互连层的其它部分。 多个第一级互连层中的每一个与第一电极层和第二电极层中的至少一个共享相同的层。

公开(公告)号：US5217914A

公开(公告)日：1993-06-08

申请号：US683603

申请日：1991-04-10

申请人： Susumu Matsumoto ,  Toshiki Yabu ,  Yoshiro Nakata ,  Naoto Matsuo ,  Shozo Okada ,  Hiroyuki Sakai

发明人： Susumu Matsumoto ,  Toshiki Yabu ,  Yoshiro Nakata ,  Naoto Matsuo ,  Shozo Okada ,  Hiroyuki Sakai

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L28/91

摘要： Disclosed is a semiconductor integrating circuit having stacked capacitor cells. Each of the cells includes an electric charge storage electrode for storing an electric charge, and a capacitor insulation film and opposite plate electrode integrated thereon. The electric charge storage electrode consists essentially of a bottom and a part in at least double frame-like portion or at least one column-like portion and at least one frame-like portion surrounding the column-like portion rising upwardly from the bottom surface. The capacitor deposited film consists of a dielectric material film deposited on all of the bottom plane and all surfaces of the charge storage electrode, and constructs a capacitor in cooperation with the opposite plate electrode. The described method for making a stacked capacitor cell can make it possible to form self-aligned capacitors by repeating a deposition of an oxide film and a conductive film and an anisotropic etching.

摘要翻译： 公开了具有层叠电容器单元的半导体积分电路。 每个单元包括用于存储电荷的电荷存储电极，以及集成在其上的电容器绝缘膜和相对的平板电极。 电荷存储电极基本上由至少双框状部分或至少一个柱状部分中的底部和部分组成，以及围绕从底面向上升起的柱状部分的至少一个框状部分。 电容器沉积膜由沉积在电荷存储电极的所有底面和所有表面上的介电材料膜构成，并与相对的板电极配合构建电容器。 所述制造叠层电容器电池的方法可以通过重复氧化膜和导电膜的沉积以及各向异性蚀刻来形成自对准电容器。

公开(公告)号：US5241201A

公开(公告)日：1993-08-31

申请号：US678150

申请日：1991-04-02

申请人： Naoto Matsuo ,  Shozo Okada ,  Susumu Matsumoto ,  Yoshiro Nakata ,  Toshiki Yabu

发明人： Naoto Matsuo ,  Shozo Okada ,  Susumu Matsumoto ,  Yoshiro Nakata ,  Toshiki Yabu

IPC分类号： H01L27/108

CPC分类号： H01L27/10817

摘要： A new semiconductor memory device for performing a read/write of information of randomly accessed address includes a plurality of memory cells put in parallel arrays. Each memory cell includes a switching transistor region and a capacitor region. The capacitor regions of the two adjacent memory cells are formed in a common region over the switching transistor region of the two adjacent memory cells. The charge storage electrode of the capacitor region has the shape of a loop. The charge storage electrodes are formed by using self-alignment.

摘要翻译： 用于执行随机访问地址的信息的读/写的新的半导体存储器件包括以并行阵列放置的多个存储单元。 每个存储单元包括开关晶体管区域和电容器区域。 两个相邻存储单元的电容器区域形成在两个相邻存储单元的开关晶体管区域上的公共区域中。 电容器区域的电荷存储电极具有环形。 电荷存储电极通过使用自对准形成。

公开(公告)号：US06570231B1

公开(公告)日：2003-05-27

申请号：US09652989

申请日：2000-08-31

申请人： Masahiro Yasumi ,  Ichirou Matsuo ,  Toshiki Yabu ,  Mizuki Segawa ,  Kunitoshi Aono ,  Akihiko Ohtani ,  Takayuki Minemaru ,  Tadashi Fukumoto

发明人： Masahiro Yasumi ,  Ichirou Matsuo ,  Toshiki Yabu ,  Mizuki Segawa ,  Kunitoshi Aono ,  Akihiko Ohtani ,  Takayuki Minemaru ,  Tadashi Fukumoto

IPC分类号： H01L2976

CPC分类号： H01L21/823842 ,  H01L21/823835 ,  H01L21/823871

摘要： An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.

摘要翻译： 形成n沟道有源区，p沟道有源区和隔离绝缘膜，通过栅极绝缘膜沉积硅膜。 在n沟道区域中引入n型杂质并将p型杂质引入p沟道区中后，形成硅栅电极，使其宽度仅在n沟道区域之间的边界部分扩大 和p沟道区域。 在形成侧壁绝缘膜，n沟道扩散层和p沟道扩散层之后，在硅栅极，n沟道扩散层和n沟道扩散层的表面上以自对准的方式形成金属硅化物层 p沟道扩散层。

公开(公告)号：US6143626A

公开(公告)日：2000-11-07

申请号：US330068

申请日：1999-06-11

申请人： Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Takashi Nakabayashi

发明人： Toshiki Yabu ,  Takashi Uehara ,  Mizuki Segawa ,  Takashi Nakabayashi

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76229

摘要： On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions. Thus, in a highly integrated semiconductor device having a trench isolation, degradation of reliability resulting from the opening of the void in the surface of isolation is prevented.

摘要翻译： 在半导体衬底上依次沉积二氧化硅膜和氮化硅膜。 使用具有对应于隔离区域的开口的光致抗蚀剂膜，依次蚀刻氮化硅膜，二氧化硅膜和半导体衬底，从而形成沟槽。 在沉积防扩散膜之后，沉积具有可回流性的用于隔离的绝缘膜。 虽然在隔离区域中用于隔离的绝缘膜中形成空隙，但是使用于隔离的绝缘膜回流，从而消除空隙。 之后，通过CMP对整个基板进行平坦化，以除去氮化硅膜和二氧化硅膜，然后在各个元件形成区域中形成栅极绝缘膜，栅极电极，侧壁和源极/漏极区域。 因此，在具有沟槽隔离的高度集成的半导体器件中，防止了由于隔离表面中的空隙的打开引起的可靠性降低。

公开(公告)号：US6083785A

公开(公告)日：2000-07-04

申请号：US874911

申请日：1997-06-16

申请人： Mizuki Segawa ,  Toshiki Yabu ,  Akira Matsuzawa

发明人： Mizuki Segawa ,  Toshiki Yabu ,  Akira Matsuzawa

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/118 ,  H01L27/02

CPC分类号： H01L28/40 ,  H01L27/0629 ,  H01L27/118 ,  H01L28/10 ,  H01L28/20

摘要： An isolation is formed in a part of a P-well of a semiconductor substrate. A resistor film as a first conductor member is formed on the isolation. An insulating film covering the resistor film except for contact formation regions and an upper electrode film as a second conductor member are formed simultaneously with the formation of a gate electrode and a gate oxide film. Silicide films of a refractory metal are formed on the respective surfaces of the gate electrode, N-type high-concentration diffusion layers, the contact formation regions of the resistor film, and the upper electrode film. By utilizing a salicide process, a resistor and an inductor each occupying a small area can be formed without lowering the resistance of the resistor film. A capacitor, the resistor, and like component are selectively allowed to function.

摘要翻译： 在半导体衬底的P阱的一部分中形成隔离。 在隔离件上形成作为第一导体部件的电阻膜。 在形成栅极电极和栅极氧化膜的同时形成覆盖除了接触形成区域之外的电阻膜的绝缘膜和作为第二导体构件的上部电极膜。 在栅电极，N型高浓度扩散层，电阻膜的接触形成区域和上电极膜的各个表面上形成难熔金属的硅化物膜。 通过利用自对准硅化物工艺，可以形成每个占据小面积的电阻器和电感器，而不降低电阻膜的电阻。 选择性地允许电容器，电阻器等组件起作用。

公开(公告)号：US5903031A

公开(公告)日：1999-05-11

申请号：US675659

申请日：1996-07-03

申请人： Takayuki Yamada ,  Takashi Nakabayashi ,  Masatoshi Arai ,  Toshiki Yabu ,  Koji Eriguchi

发明人： Takayuki Yamada ,  Takashi Nakabayashi ,  Masatoshi Arai ,  Toshiki Yabu ,  Koji Eriguchi

IPC分类号： H01L21/3213 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/76838 ,  H01L21/32136

摘要： In a first region of a semiconductor substrate, there are formed MIS transistors each composed of a gate insulating film, a gate electrode, and source/drain regions. In a second region of the semiconductor substrate, there is formed an impurity diffusion layer serving as a conductive layer. On an interlayer insulating film, there are formed an antenna interconnection connected to the gate electrodes and an interconnection for charge dissipation connected to the conductive layer. During the process of dry etching for forming the interconnections, charges move into the semiconductor substrate via the interconnection for charge dissipation. The deterioration of the gate insulating film caused by the injection of charges into the gate electrode is suppressed and the degradation of characteristics of the MIS transistor including a shift in threshold is also suppressed. Even in the case where a floating interconnection region is present contiguously to the antenna interconnection, the provision of the interconnection for charge dissipation reduces the amount of shift in the threshold of each of the MIS transistors and equalizes the respective thresholds of the MIS transistors.

摘要翻译： 在半导体基板的第一区域中，形成有由栅极绝缘膜，栅极电极和源极/漏极区域构成的MIS晶体管。 在半导体衬底的第二区域中，形成用作导电层的杂质扩散层。 在层间绝缘膜上形成连接到栅电极的天线布线和连接到导电层的用于电荷耗散的互连。 在用于形成互连的干蚀刻过程中，电荷通过互连进入半导体衬底以进行电荷耗散。 抑制了通过向栅电极注入电荷而导致的栅极绝缘膜的劣化，并且也抑制了包括阈值偏移的MIS晶体管的特性劣化。 即使在浮动互连区域与天线互连连续地存在的情况下，提供用于电荷耗散的互连减少了每个MIS晶体管的阈值偏移量，并且均衡了MIS晶体管的各个阈值。

公开(公告)号：US5270226A

公开(公告)日：1993-12-14

申请号：US332714

申请日：1989-04-03

申请人： Takashi Hori ,  Toshiki Yabu ,  Kazumi Kurimoto ,  Genshu Fuse

发明人： Takashi Hori ,  Toshiki Yabu ,  Kazumi Kurimoto ,  Genshu Fuse

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7836

摘要： By symmetrically forming source and drain regions to the gate electrodes, electrically symmetrical transistor characteristics are obtained. After forming the first source and drain regions by large-tilt-angle ion implantation, without a sidewall in the gate electrode or after forming a sidewall shorter than the distance in the lateral direction of the second source and drain regions from the end of the mask for ion implantation, the diffusion of the second source and drain regions in the lateral direction is restricted to the maximum extent by heat treatment for a short time, and then the end of the gate electrode and the end of the second source and drain regions are matched, or their overlap region is formed. As a result, the manufacturing method of the MOS transistor results in both high performance and high reliability.

摘要翻译： 通过对栅极对称地形成源极和漏极区域，获得电对称的晶体管特性。 在通过大倾斜角度离子注入形成第一源极和漏极区域之后，在栅电极中没有侧壁或在形成比第二源极和漏极区域的横向方向上距离掩模的端部短的侧壁 对于离子注入，第二源极和漏极区域在横向上的扩散通过短时间的热处理被限制在最大程度，然后栅电极的端部和第二源极和漏极区域的端部是 匹配，或者形成它们的重叠区域。 结果，MOS晶体管的制造方法具有高性能和高可靠性。

公开(公告)号：US20050093089A1

公开(公告)日：2005-05-05

申请号：US10995283

申请日：2004-11-24

申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/00

CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

摘要翻译： 形成了比硅衬底的有源区域更高级的隔离。 在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。 绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。 不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。 由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。 以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。