公开(公告)号：US08648441B2

公开(公告)日：2014-02-11

申请号：US13106590

申请日：2011-05-12

申请人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Kenichiro Hijioka ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L21/02

CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

公开(公告)号：US08629529B2

公开(公告)日：2014-01-14

申请号：US12519706

申请日：2007-12-25

申请人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Naoya Inoue ,  Ippei Kume ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L27/06

CPC分类号： H01L23/5228 ,  H01L23/5223 ,  H01L23/53238 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is produced by fabricating a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, and a thin-film resistor element, in the same step. As the lower electrode of the capacitor element is lined with a lower layer wiring layer (Cu wiring), the lower electrode has extremely low resistance substantially. As such, even if the film thickness of the lower electrode becomes thinner, parasitic resistance does not increased. The resistor element is formed to have the same film thickness as that of the lower electrode of the capacitor element. Since the film thickness of the lower electrode is thin, it works as a resistor having high resistance. In the top layer of the passive element, a passive element cap insulating film is provided, which works as an etching stop layer when etching a contact of the upper electrode of the capacitor element.

摘要翻译： 通过在同一步骤中制造包括下电极，电容器绝缘膜和上电极的电容器元件和薄膜电阻器元件来制造半导体器件。 由于电容器元件的下电极衬有下层布线层（Cu布线），所以下电极具有极低的电阻。 因此，即使下电极的膜厚变薄，寄生电阻也不会增加。 电阻元件形成为具有与电容器元件的下电极相同的膜厚度。 由于下部电极的膜厚薄，所以作为具有高电阻的电阻器。 在无源元件的顶层中，设置无源元件帽绝缘膜，当蚀刻电容器元件的上电极的接触时，其被用作蚀刻停止层。

公开(公告)号：US08618537B2

公开(公告)日：2013-12-31

申请号：US13067386

申请日：2011-05-27

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/10

CPC分类号： H01L29/7869 ,  H01L27/0688 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/45 ,  H01L29/458

摘要： A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.

摘要翻译： 半导体器件包括在半导体衬底上的第一区域中，第一绝缘层，第一布线，第二绝缘层，第三绝缘层以及嵌入第二绝缘层中的通孔和第二布线，以及第三绝缘层 并且在第二区域中包括第一绝缘层，栅电极，第二绝缘层，位于第三绝缘层和第一导电体中的半导体层，以及嵌入在第二绝缘层中的第二导电体 第三绝缘层，以通过势垒金属在平面图中将栅电极夹在与半导体层重叠的位置，并通过阻挡金属耦合到半导体层。

公开(公告)号：US20120228728A1

公开(公告)日：2012-09-13

申请号：US13399475

申请日：2012-02-17

申请人： Makoto UEKI ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Makoto UEKI ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

摘要： A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

摘要翻译： 一种半导体器件，其中在包含在多层布线层中的布线层A中形成MRAM，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化 层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。

公开(公告)号：US20120115253A1

公开(公告)日：2012-05-10

申请号：US13373098

申请日：2011-11-04

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L43/12

CPC分类号： H01L23/552 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material.

摘要翻译： 一种半导体装置的制造方法，其特征在于，在基板的主面上形成半导体装置，所述半导体装置具有互连层，形成覆盖所述半导体装置的缓冲膜，防止磁性材料的扩散，形成 覆盖缓冲膜并包括磁性材料的磁屏蔽膜。

公开(公告)号：US20110284991A1

公开(公告)日：2011-11-24

申请号：US13106590

申请日：2011-05-12

申请人： Kenichiro HIJIOKA ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

发明人： Kenichiro HIJIOKA ,  Ippei Kume ,  Naoya Inoue ,  Hiroki Shirai ,  Jun Kawahara ,  Yoshihiro Hayashi

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L27/10894 ,  H01L21/76811 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/75 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a substrate; a multi-layered interconnect formed on the substrate, and having a plurality of interconnect layers, each of which being configured by an interconnect and an insulating layer, stacked therein; a memory circuit formed in a memory circuit region on the substrate in a plan view, and having a peripheral circuit and at least one capacitor element embedded in the multi-layered interconnect; and a logic circuit formed in a logic circuit region on the substrate, wherein the capacitor element is configured by a lower electrode, a capacitor insulating film, an upper electrode, an embedded electrode and an upper interconnect; the top surface of the upper interconnect, and the top surface of the interconnect configuring the logic circuit formed in the same interconnect layer with the upper interconnect, are aligned to the same plane.

摘要翻译： 半导体器件具有基板; 形成在所述基板上的多层互连，并且具有多个互连层，每个互连层由布置在其中的互连和绝缘层构成; 在平面图形成在基板上的存储器电路区域中的存储电路，并且具有外围电路和嵌入多层互连中的至少一个电容元件; 以及形成在所述基板上的逻辑电路区域中的逻辑电路，其中所述电容器元件由下电极，电容器绝缘膜，上电极，嵌入电极和上互连构成; 上互连的顶表面和构成与上互连的同一互连层中形成的逻辑电路的互连的顶表面与同一平面对准。

公开(公告)号：US20100327409A1

公开(公告)日：2010-12-30

申请号：US12864091

申请日：2009-01-22

申请人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Ippei Kume ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/92 ,  H01L21/314

CPC分类号： H01L28/60 ,  H01L21/28506 ,  H01L21/31637 ,  H01L21/32053 ,  H01L21/32105 ,  H01L23/5223 ,  H01L23/5283 ,  H01L23/5286 ,  H01L27/0688 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film.

摘要翻译： 形成在半导体器件内的电容元件包括上电极，含有过渡金属元素的氧化物和/或硅酸盐的电容绝缘膜，以及具有多晶导电膜的下电极，所述多晶导体膜由比所述转变 金属元素和形成在多晶导电膜下面的非晶或微晶导电膜。

公开(公告)号：US20100148171A1

公开(公告)日：2010-06-17

申请号：US12654205

申请日：2009-12-14

申请人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

发明人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

摘要： A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

摘要翻译： 本发明的半导体器件具有形成在半导体衬底上的第一互连层和半导体元件; 所述第一互连层具有绝缘层，以及填充在所述绝缘层的表面部分中的第一互连层; 半导体元件具有半导体层，栅极绝缘膜和栅电极; 半导体层位于第一互连层上方; 栅绝缘膜位于半导体层之上或之下; 并且栅极电极位于半导体层的相反侧，同时将栅极绝缘膜放置在其间。

公开(公告)号：US06174766B1

公开(公告)日：2001-01-16

申请号：US09098436

申请日：1998-06-17

申请人： Yoshihiro Hayashi ,  Naoya Inoue ,  Sota Kobayashi

发明人： Yoshihiro Hayashi ,  Naoya Inoue ,  Sota Kobayashi

IPC分类号： H01L2976

CPC分类号： H01L28/55 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device which ensures the reliability of the connection between a metal wiring of the device to a MOS transistor of the device and which enables the metal wiring to be connected to an electrode of a capacitor of the device without any deteriorating a metal oxide dielectric film of the capacitor is provided. In the method, a transistor having a source/drain region and a gate electrode is formed on a semiconductor substrate. Then, a capacitor is formed on the substrate and has an upper capacitor electrode, a lower capacitor electrode, and a metallic oxide dielectric film disposed between the upper capacitor electrode and the lower capacitor electrode. An insulating film is formed over the capacitor such that the insulating film covers the capacitor, and a transistor contact hole is formed through the insulating film for providing an electrical connection to the transistor while the capacitor is covered via the insulating film and not exposed to an atmosphere when the first contact hole is formed. Also, a capacitor contact hole is formed through the insulating film for providing an electrical connection to the capacitor after the transistor contact hole is formed. A device manufactured by the above method is also provided.

摘要翻译： 一种制造半导体器件的方法，其确保器件的金属布线与器件的MOS晶体管之间的连接的可靠性，并且能够使金属布线连接到器件的电容器的电极而不会劣化 提供电容器的金属氧化物介电膜。 在该方法中，在半导体衬底上形成具有源极/漏极区域和栅电极的晶体管。 然后，在基板上形成电容器，具有设置在上部电容电极和下部电容器电极之间的上部电容电极，下部电容电极和金属氧化物电介质膜。 在电容器上形成绝缘膜，使得绝缘膜覆盖电容器，并且通过绝缘膜形成晶体管接触孔，用于在晶体管提供电连接的同时，通过绝缘膜覆盖电容器，而不暴露于 形成第一接触孔时的气氛。 此外，在形成晶体管接触孔之后，通过绝缘膜形成电容器接触孔，以提供与电容器的电连接。 还提供了通过上述方法制造的装置。

公开(公告)号：US08558334B2

公开(公告)日：2013-10-15

申请号：US13399475

申请日：2012-02-17

申请人： Makoto Ueki ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Makoto Ueki ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/82 ,  H01L23/552 ,  H01L27/08 ,  H01L21/00

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/08

摘要： A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer.

摘要翻译： 一种半导体器件，其中MRAM形成在包含在多层布线层中的布线层A中，所述MRAM具有与形成在布线层中并彼此绝缘的第一布线接触的至少两个第一磁化闭塞层，自由磁化 层在平面图中与两个第一磁化钉扎层重叠，并与第一磁化钉扎层，位于自由磁化层上方的非磁性层和位于非磁性层上的第二磁化钉扎层连接。