公开(公告)号：US08373256B2

公开(公告)日：2013-02-12

申请号：US12770050

申请日：2010-04-29

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L23/552

CPC分类号： H01L23/552 ,  H01L23/5225 ,  H01L23/5227 ,  H01L27/228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on a principal surface of the semiconductor substrate and having a multiple-layered interconnect layer; and a heterostructure magnetic shield covering the semiconductor element. The heterostructure magnetic shield includes a first magnetic shield layered structure and a second magnetic shield layered structure that covers the first magnetic shield layered structure. Each of a first and a second magnetic shield layered structures includes a magnetic shielding film composed of a magnetic substance and covering the semiconductor element and a buffer film disposed between the semiconductor element and the magnetic shield films and preventing a diffusion of the magnetic substance.

摘要翻译： 半导体器件包括：半导体衬底; 半导体元件，其形成在所述半导体衬底的主表面上并具有多层互连层; 和覆盖半导体元件的异质结构磁屏蔽。 异质结构磁屏蔽包括第一磁屏蔽分层结构和覆盖第一磁屏蔽分层结构的第二磁屏蔽分层结构。 第一和第二磁屏蔽分层结构中的每一个包括由磁性物质构成并覆盖半导体元件的磁屏蔽膜和设置在半导体元件和磁屏蔽膜之间的缓冲膜，并且防止磁性物质的扩散。

公开(公告)号：US20100207093A1

公开(公告)日：2010-08-19

申请号：US12656728

申请日：2010-02-16

申请人： Naoya Inoue ,  Yoshihiro Hayashi ,  Kishou Kaneko

发明人： Naoya Inoue ,  Yoshihiro Hayashi ,  Kishou Kaneko

IPC分类号： H01L45/00 ,  H01L21/441

CPC分类号： H01L21/76807 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

摘要： Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

摘要翻译： 提供了一种半导体器件，其包括基板，以及形成在基板上的第一布线层，第二布线层和开关通孔。 第一布线层具有形成在其中的第一布线，并且第二布线层具有形成在其中的第二布线。 开关通孔连接第一布线和第二布线。 开关通孔至少在其底部包括包括电阻变化层的开关元件。 电阻变化层的电阻值根据施加到其上的电场的历史而变化。

公开(公告)号：US08378341B2

公开(公告)日：2013-02-19

申请号：US12654205

申请日：2009-12-14

申请人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

发明人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

IPC分类号： H01L29/18 ,  H01L21/00

CPC分类号： H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

摘要： A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

摘要翻译： 本发明的半导体器件具有形成在半导体衬底上的第一互连层和半导体元件; 所述第一互连层具有绝缘层，以及填充在所述绝缘层的表面部分中的第一互连层; 半导体元件具有半导体层，栅极绝缘膜和栅电极; 半导体层位于第一互连层上方; 栅绝缘膜位于半导体层之上或之下; 并且栅极电极位于半导体层的相反侧，同时将栅极绝缘膜放置在其间。

公开(公告)号：US08618537B2

公开(公告)日：2013-12-31

申请号：US13067386

申请日：2011-05-27

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L29/10

CPC分类号： H01L29/7869 ,  H01L27/0688 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/45 ,  H01L29/458

摘要： A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal.

摘要翻译： 半导体器件包括在半导体衬底上的第一区域中，第一绝缘层，第一布线，第二绝缘层，第三绝缘层以及嵌入第二绝缘层中的通孔和第二布线，以及第三绝缘层 并且在第二区域中包括第一绝缘层，栅电极，第二绝缘层，位于第三绝缘层和第一导电体中的半导体层，以及嵌入在第二绝缘层中的第二导电体 第三绝缘层，以通过势垒金属在平面图中将栅电极夹在与半导体层重叠的位置，并通过阻挡金属耦合到半导体层。

公开(公告)号：US20120115253A1

公开(公告)日：2012-05-10

申请号：US13373098

申请日：2011-11-04

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L43/12

CPC分类号： H01L23/552 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material.

摘要翻译： 一种半导体装置的制造方法，其特征在于，在基板的主面上形成半导体装置，所述半导体装置具有互连层，形成覆盖所述半导体装置的缓冲膜，防止磁性材料的扩散，形成 覆盖缓冲膜并包括磁性材料的磁屏蔽膜。

公开(公告)号：US20100148171A1

公开(公告)日：2010-06-17

申请号：US12654205

申请日：2009-12-14

申请人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

发明人： Yoshihiro Hayashi ,  Naoya Inoue ,  Kishou Kaneko

IPC分类号： H01L29/24 ,  H01L21/336

CPC分类号： H01L21/76807 ,  H01L21/28282 ,  H01L21/76877 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/242 ,  H01L29/41 ,  H01L29/42344 ,  H01L29/42352 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/792

摘要： A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

摘要翻译： 本发明的半导体器件具有形成在半导体衬底上的第一互连层和半导体元件; 所述第一互连层具有绝缘层，以及填充在所述绝缘层的表面部分中的第一互连层; 半导体元件具有半导体层，栅极绝缘膜和栅电极; 半导体层位于第一互连层上方; 栅绝缘膜位于半导体层之上或之下; 并且栅极电极位于半导体层的相反侧，同时将栅极绝缘膜放置在其间。

公开(公告)号：US09263399B2

公开(公告)日：2016-02-16

申请号：US14002548

申请日：2012-03-06

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L23/552 ,  H01L27/02 ,  H01L27/06 ,  H01L27/12 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L27/0285 ,  H01L23/522 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0688 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/24 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.

摘要翻译： 半导体器件包括其上形成半导体器件的半导体衬底; 第一和第二垫; 形成在半导体衬底上的第一绝缘膜; 埋设在第一绝缘膜中的沟槽中的多条布线; 设置为覆盖所述第一绝缘膜和所述多条布线的第二绝缘膜; 形成在所述第二绝缘膜上的半导体层; 与半导体层连接的源电极; 以及与半导体层连接的漏电极。 多个布线包括设置在与半导体层相对的位置的栅电极。 半导体层，源电极，漏电极和栅电极构成ESD保护器件，以通过ESD浪涌从第一焊盘向第二焊盘放电。

公开(公告)号：US09035360B2

公开(公告)日：2015-05-19

申请号：US13610241

申请日：2012-09-11

申请人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

发明人： Kishou Kaneko ,  Naoya Inoue ,  Yoshihiro Hayashi

IPC分类号： H01L23/52 ,  H01L27/06 ,  H01L21/822

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2924/00012

摘要： A semiconductor device includes a logic circuit and an active element circuit. The logic circuit is provided with semiconductor elements formed in a semiconductor substrate. The active element circuit is provided with transistors formed using semiconductor layers formed over a diffusion insulating film formed above a semiconductor substrate. The active element circuit is controlled by the logic circuit.

摘要翻译： 半导体器件包括逻辑电路和有源元件电路。 逻辑电路设置有形成在半导体衬底中的半导体元件。 有源元件电路设置有使用在半导体衬底上形成的扩散绝缘膜上形成的半导体层形成的晶体管。 有源元件电路由逻辑电路控制。

公开(公告)号：US08390124B2

公开(公告)日：2013-03-05

申请号：US12656728

申请日：2010-02-16

申请人： Naoya Inoue ,  Yoshihiro Hayashi ,  Kishou Kaneko

发明人： Naoya Inoue ,  Yoshihiro Hayashi ,  Kishou Kaneko

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/32 ,  H01L29/74 ,  H01L31/111 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L21/76807 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633

摘要： Provided is a semiconductor device including a substrate, and a first wiring layer, a second wiring layer, and a switch via formed on the substrate. The first wiring layer has first wiring formed therein and the second wiring layer has second wiring formed therein. The switch via connects the first wiring and the second wiring. The switch via includes at least at its bottom a switch element including a resistance change layer. A resistance value of the resistance change layer changes according to a history of an electric field applied thereto.

摘要翻译： 提供了一种半导体器件，其包括基板，以及形成在基板上的第一布线层，第二布线层和开关通孔。 第一布线层具有形成在其中的第一布线，并且第二布线层具有形成在其中的第二布线。 开关通孔连接第一布线和第二布线。 开关通孔至少在其底部包括包括电阻变化层的开关元件。 电阻变化层的电阻值根据施加到其上的电场的历史而变化。

公开(公告)号：US08901553B2

公开(公告)日：2014-12-02

申请号：US13476468

申请日：2012-05-21

申请人： Naoya Inoue ,  Kishou Kaneko ,  Yoshihiro Hayashi

发明人： Naoya Inoue ,  Kishou Kaneko ,  Yoshihiro Hayashi

IPC分类号： H01L21/336 ,  H01L29/12 ,  H01L29/78 ,  H01L29/786 ,  H01L21/768 ,  H01L23/532 ,  H01L27/12 ,  H01L23/522 ,  H01L29/423

CPC分类号： H01L29/42384 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02565 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention makes it possible to lower the on resistance of a semiconductor element without hindering the function of a diffusion prevention film in a semiconductor device having the semiconductor element that uses a wire in a wiring layer as a gate electrode and has a gate insulation film in an identical layer to the diffusion prevention film. A first wire and a gate electrode are embedded into the surface layer of an insulation layer comprising a first wiring layer. A diffusion prevention film is formed between the first wiring layer and a second wiring layer. A gate insulation film is formed by: forming a recess over the upper face of the diffusion prevention film in the region overlapping with the gate electrode and around the region; and thinning the part.

摘要翻译： 本发明可以降低半导体元件的导通电阻，而不会妨碍具有使用布线层中的导线的半导体元件作为栅电极的半导体器件中的扩散防止膜的功能，并具有栅极绝缘膜 在与扩散防止膜相同的层中。 第一导线和栅电极嵌入到包括第一布线层的绝缘层的表面层中。 在第一布线层和第二布线层之间形成扩散防止膜。 栅极绝缘膜通过以下方式形成：在与栅电极重叠的区域和区域周围形成在扩散防止膜的上表面上的凹部; 并使部件变薄。