公开(公告)号：US08445352B2

公开(公告)日：2013-05-21

申请号：US12268538

申请日：2008-11-11

申请人： Natsuki Yokoyama ,  Tomoyuki Someya

发明人： Natsuki Yokoyama ,  Tomoyuki Someya

IPC分类号： H01L21/331

CPC分类号： H01L21/02378 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/513 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/7828 ,  H01L29/8611 ,  H01L29/872

摘要： A problem in the conventional technique is that metal contamination on a silicon carbide surface is not sufficiently removed in a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate. Accordingly, there is a high possibility that the initial characteristics of a manufactured silicon carbide semiconductor device are deteriorated and the yield rate is decreased. Further, it is conceivable that the metal contamination has an adverse affect even on the long-term reliability of a semiconductor device. In a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate, there is applied a metal contamination removal process, on a silicon carbide surface, including a step of oxidizing the silicon carbide surface and a step of removing a film primarily including silicon dioxide formed on the silicon carbide surface by the step.

摘要翻译： 在常规技术中的问题在于，在使用单晶碳化硅基板的半导体器件的制造方法中，在碳化硅表面上的金属污染没有被充分地去除。 因此，制造的碳化硅半导体器件的初始特性可能会降低，成品率降低。 此外，可以想到，即使对于半导体器件的长期可靠性，金属污染也具有不利影响。 在使用单晶硅碳化物衬底的半导体器件的制造方法中，在碳化硅表面上应用金属污染去除工艺，包括氧化碳化硅表面的步骤和去除主要包括二氧化硅的膜的步骤 通过该步骤在碳化硅表面上形成。

公开(公告)号：US5940272A

公开(公告)日：1999-08-17

申请号：US904862

申请日：1997-08-01

申请人： Akihiko Emori ,  Hiroyuki Hanei ,  Tsunehiro Endo ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama ,  Kazuo Kato

发明人： Akihiko Emori ,  Hiroyuki Hanei ,  Tsunehiro Endo ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama ,  Kazuo Kato

IPC分类号： H02B1/56 ,  H02M7/00 ,  H02M7/04 ,  H02M7/48 ,  H02P27/06 ,  H05K7/14 ,  H05K7/20

CPC分类号： H05K7/20927 ,  H02M7/003 ,  H01L2924/1616

摘要： An electric apparatus has a plurality of electric parts and a casing made of electrically conductive material for accommodating therein or mounting thereon a plurality of electric parts. The casing, which has a cavity therein, is provided with a plurality of projections for radiating heat generated by the electric parts in the cavity. The casing is provided with openings for allowing a heat conductive medium to flow into and out of the casing. Further, an electric apparatus has a plurality of electric parts and a casing made of electrically conductive material for accommodating therein or mounting thereon a plurality of electric parts. The casing is provided with openings for allowing a heat conductive medium to flow into and out of the casing. The casing is provided therein with a partition wall which is made of electrically conductive material for dividing the interior of the casing into a plurality of zones along a direction of a flow of the heat conductive medium.

摘要翻译： 电气设备具有多个电气部件和由导电材料制成的壳体，用于容纳其中或安装有多个电气部件。 在其中具有空腔的壳体设置有用于散发由腔中的电气部件产生的热量的多个突起。 壳体设置有用于允许导热介质流入和流出壳体的开口。 此外，电气设备具有多个电气部件和由导电材料制成的壳体，用于容纳其中或安装有多个电气部件。 壳体设置有用于允许导热介质流入和流出壳体的开口。 壳体设置有分隔壁，该分隔壁由导电材料制成，用于将壳体的内部沿着导热介质的流动方向分成多个区域。

公开(公告)号：US5268587A

公开(公告)日：1993-12-07

申请号：US786750

申请日：1991-11-01

申请人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

发明人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

IPC分类号： H01L27/105 ,  H01L27/108 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/10805 ,  H01L27/105

摘要： A semiconductor integrated circuit device includes a dielectric breakdown prevention circuit coupled to an external terminal for protecting an input stage circuit. The prevention circuit has bipolar transistors and complementary MISFETs including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type. A first semiconductor region of the first conductivity type is formed by the same layer as a well region in which the second MISFET is formed. A second semiconductor region of the second conductivity type is formed in said first semiconductor region by the same layer as source and drain regions of the second MISFET. These first and second semiconductor regions form a first PN junction diode. The external terminal is electrically coupled to one end portion of said second semiconductor region. A high impurity conductivity type buried third semiconductor region underlies the said second semiconductor region, and is formed by the same layer as a region isolating the bipolar transistors. This third region is disposed at the bottom surface of said first semiconductor region. A fourth semiconductor region of the second conductivity type is also formed in said first semiconductor region by the same layer used for collector contact regions of the bipolar transistors, and is connected with another end portion of said second semiconductor region, in contact with the third semiconductor region. The fourth semiconductor region is coupled to the input stage circuit, and the third and fourth semiconductor regions form a second PN junction diode.

摘要翻译： 半导体集成电路器件包括耦合到外部端子的绝缘击穿防止电路，用于保护输入级电路。 防止电路具有双极晶体管和互补MISFET，其包括第一导电类型的第一MISFET和第二导电类型的第二MISFET。 第一导电类型的第一半导体区域由与其中形成第二MISFET的阱区相同的层形成。 第二导电类型的第二半导体区域通过与第二MISFET的源极和漏极区域相同的层在所述第一半导体区域中形成。 这些第一和第二半导体区域形成第一PN结二极管。 外部端子电耦合到所述第二半导体区域的一个端部。 高杂质导电型掩埋的第三半导体区域位于所述第二半导体区域的下方，并且由与隔离双极晶体管的区域相同的层形成。 该第三区域设置在所述第一半导体区域的底表面。 第二导电类型的第四半导体区域也通过与用于双极晶体管的集电极接触区域的相同的层形成在所述第一半导体区域中，并且与所述第二半导体区域的与第三半导体接触的另一个端部连接 地区。 第四半导体区域耦合到输入级电路，并且第三和第四半导体区域形成第二PN结二极管。

公开(公告)号：US5734616A

公开(公告)日：1998-03-31

申请号：US694059

申请日：1996-08-08

申请人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

发明人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

IPC分类号： G11C11/419 ,  G11C7/00

CPC分类号： G11C11/419

摘要： A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.

摘要翻译： 静态RAM包括前置放大器，其仅由具有其电源电压的集电极的射极跟随器晶体管组成，与通过列开关连接到互补数据线的子公共数据线对一一对应 成对的存储器阵列。 前置放大器设置有在选择状态期间导通的第一开关，以将子公共数据线对连接到晶体管的基极;以及第二开关，其在未选择状态期间导通，以向基极提供一定的偏置 电压低于副公共数据线对上的读出信号电压。 射极跟随器晶体管的发射极共同连接形成共同的发射极线，其连接到由CMOS晶体管构成的主放大器的输入端对。

公开(公告)号：US5081515A

公开(公告)日：1992-01-14

申请号：US496328

申请日：1990-03-20

申请人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

发明人： Jun Murata ,  Hideyuki Miyazawa ,  Kyoichiro Asayama ,  Akihiro Tamba ,  Seigou Yukutake ,  Hiroyuki Miyazawa ,  Yutaka Kobayashi ,  Tomoyuki Someya

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8242 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/732

CPC分类号： H01L27/10805 ,  H01L27/105

摘要： A semiconductor integrated circuit device is equipped with a DRAM whose memory cell is formed as a series circuit of a memory cell selection MISFET and a data storage capacitance element of a stacked structure. A complementary data line extends on an upper electrode layer of the data storage capacitance element of the stacked structure through an inter-level insulation film which is connected to a semiconductor region of the memory cell selection MISFET. To reduce parasitic capacitance the wiring width of the complementary data line is formed to be smaller than the film thickness of the inter-level insulation film between the complementary data line and the upper electrode layer of said data storage capacitance element of the stacked structure.

摘要翻译： 半导体集成电路器件配备有DRAM，其存储单元形成为存储单元选择MISFET和层叠结构的数据存储电容元件的串联电路。 互补数据线通过连接到存储单元选择MISFET的半导体区域的层间绝缘膜在层叠结构的数据存储电容元件的上电极层上延伸。 为了减小寄生电容，互补数据线的布线宽度形成为小于互补数据线与层叠结构的数据存储电容元件的上电极层之间的层间绝缘膜的膜厚度。