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17 条记录 (耗时 0.046 秒)

    Semiconductor memory device and sense circuit
    1.
    发明授权
    Semiconductor memory device and sense circuit 失效
    半导体存储器件和感测电路

    公开(公告)号：US5734616A

    公开(公告)日：1998-03-31

    申请号：US694059

    申请日：1996-08-08

    申请人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

    发明人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

    IPC分类号： G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419

    摘要： A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.

    摘要翻译： 静态RAM包括前置放大器，其仅由具有其电源电压的集电极的射极跟随器晶体管组成，与通过列开关连接到互补数据线的子公共数据线对一一对应 成对的存储器阵列。 前置放大器设置有在选择状态期间导通的第一开关，以将子公共数据线对连接到晶体管的基极;以及第二开关，其在未选择状态期间导通，以向基极提供一定的偏置 电压低于副公共数据线对上的读出信号电压。 射极跟随器晶体管的发射极共同连接形成共同的发射极线，其连接到由CMOS晶体管构成的主放大器的输入端对。

    Semiconductor integrated circuit device with power consumption reducing arrangement
    3.
    发明授权
    Semiconductor integrated circuit device with power consumption reducing arrangement 失效
    具有降低功耗的半导体集成电路设备

    公开(公告)号：US5111432A

    公开(公告)日：1992-05-05

    申请号：US492329

    申请日：1990-03-12

    申请人： Shuichi Miyaoka

    发明人： Shuichi Miyaoka

    IPC分类号： G11C11/414 ,  G11C7/00 ,  G11C7/10 ,  G11C11/34 ,  G11C11/413 ,  G11C11/419

    CPC分类号： G11C7/1057 ,  G11C11/413 ,  G11C7/00 ,  G11C7/1051

    摘要： In semiconductor circuits, and particularly in memories, it is often desirable to use bipolar transistors for speed together with MOS elements. However, although the bipolar transistors are useful for speed considerations, they undesirably significantly increase the power consumption of the overall circuit. Accordingly, to reduce power consumption, a bipolar/MOSFET arrangement is provided wherein MOSFETs are used as current sources to supply operation currents to the bipolar transistors only during the periods of their operation. Thus, a semiconductor integrated circuit device is achieved featuring a high operation speed yet consuming reduced amounts of electric power. Additionally, power consumption can be further reduced by providing a time serial operation for actuation of the MOSFETs in different peripheral circuits for a memory array.

    摘要翻译： 在半导体电路中，特别是在存储器中，通常希望与MOS元件一起使用双极晶体管。 然而，虽然双极晶体管对于速度考虑是有用的，但是它们不利地显着增加了整个电路的功耗。 因此，为了降低功耗，提供了一种双极/ MOSFET布置，其中MOSFET仅在其工作期间用作电流源以向双极型晶体管提供工作电流。 因此，实现了具有高操作速度但消耗减少的电力量的半导体集成电路器件。 此外，通过提供用于在用于存储器阵列的不同外围电路中的MOSFET的驱动的时间串行操作，可以进一步降低功耗。

    Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device
    4.
    发明授权
    Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device 失效
    半导体集成电路器件，半导体集成电路器件的测试方法和半导体集成电路器件的制造方法

    公开(公告)号：US07162671B2

    公开(公告)日：2007-01-09

    申请号：US10918421

    申请日：2004-08-16

    申请人： Masatoshi Hasegawa ,  Shuichi Miyaoka ,  Hiroshi Akasaki ,  Masahiro Katayama

    发明人： Masatoshi Hasegawa ,  Shuichi Miyaoka ,  Hiroshi Akasaki ,  Masahiro Katayama

    IPC分类号： G11C29/00

    CPC分类号： G11C29/48 ,  G11C11/401 ,  G11C11/41 ,  G11C29/14 ,  G11C29/50 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Inputs of a control circuit are connected to a terminal to which an external operation control signal is supplied and a terminal to which a timing signal used exclusively for testing is supplied, and the control circuit is made controllable such that, in a test mode, a state of an internal operation control signal is changed in response to a change of a state of the external operation control signal, and the internal operation control signal is changed in response to the timing exclusively used for testing, whereas, in a normal operation mode, the state of the internal operation control signal is changed in response to the change of the state of the external operation control signal, and the internal operation control signal is changed in response to the change of the external operation control signal.

    摘要翻译： 控制电路的输入连接到提供外部操作控制信号的端子和提供专用于测试的定时信号的端子，并且控制电路被制成可控制，使得在测试模式中， 内部操作控制信号的状态响应于外部操作控制信号的状态的改变而改变，并且内部操作控制信号响应于专门用于测试的定时而改变，而在正常操作模式中， 响应于外部操作控制信号的状态的改变而改变内部操作控制信号的状态，并且内部操作控制信号响应于外部操作控制信号的改变而改变。

    Semiconductor integrated circuit device
    5.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US06735129B2

    公开(公告)日：2004-05-11

    申请号：US10153525

    申请日：2002-05-24

    申请人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

    发明人： Hiroshi Akasaki ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Masatoshi Hasegawa ,  Kozaburo Kurita

    IPC分类号： G11C700

    CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/104

    摘要： In a semiconductor integrated circuit device that includes macro cells (circuit blocks that can be designed independently) such as a storage circuit and operates synchronously with an external clock, total delay time from signal input to output is reduced and the speed of operation is increased. In the semiconductor integrated circuit device which has plural circuit blocks coupled in series for signal transmission and whose whole operation is controlled by a clock signal, the semiconductor integrated circuit device including first circuit blocks that receive input signals in response to a first timing signal based on a clock signal, and a second circuit block that forms output signals in response to a second timing signal based on the clock signal, a time difference between the first timing signal and the second timing signal is set to a non-integral multiple of the cycle of the clock signal.

    摘要翻译： 在包括诸如存储电路的宏单元（可独立设计的电路块）并且与外部时钟同步地操作的半导体集成电路器件中，从信号输入到输出的总延迟时间减少，并且操作速度增加。 在具有串联耦合用于信号传输并且其整个操作由时钟信号控制的多个电路块的半导体集成电路器件中，半导体集成电路器件包括响应于基于第一定时信号接收输入信号的第一电路块 时钟信号和响应于基于时钟信号的第二定时信号形成输出信号的第二电路块，第一定时信号和第二定时信号之间的时间差被设置为该周期的非整数倍 的时钟信号。

    Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers
    8.
    发明授权
    Semiconductor integrated circuit device having stabilizing capacitors connected between power lines of main amplifiers 有权
    半导体集成电路器件具有连接在主放大器的电源线之间的稳定电容器

    公开(公告)号：US06191990B1

    公开(公告)日：2001-02-20

    申请号：US09507785

    申请日：2000-02-22

    申请人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

    发明人： Nobutaka Itoh ,  Shuichi Miyaoka ,  Yuji Yokoyama ,  Michiaki Nakayama ,  Mitsugu Kusunoki ,  Kazumasa Takashima ,  Hideki Sakakibara ,  Toru Kobayashi

    IPC分类号： G11C702

    CPC分类号： G11C7/18 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10897 ,  H01L27/11 ,  H01L28/75

    摘要： A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

    摘要翻译： 一种半导体集成电路器件具有存储器阵列，该存储器阵列包括将读出放大器中的动态存储单元读出的小电压放大到位线和选择位线的列开关MOSFET的读出放大器的MOSFET，包括用于读出的主放大器的读/写部分 来自由列开关选择的存储器单元的存储数据，以及实现与读/写部分的数据的输入/输出操作的逻辑电路。 两个电容器具有第一电极，其对应于具有与动态存储单元的存储电容器相同结构的平板电极的第一电极和作为存储电容器的多个共同连接的存储节点的第二电极串联连接设置 到读/写部分，并连接在读/写部分的操作电压线之间。

    Semiconductor integrated circuit device
    9.
    发明授权
    Semiconductor integrated circuit device 失效

    公开(公告)号：US07023749B2

    公开(公告)日：2006-04-04

    申请号：US11040030

    申请日：2005-01-24

    申请人： Masatoshi Hasegawa ,  Shuichi Miyaoka

    发明人： Masatoshi Hasegawa ,  Shuichi Miyaoka

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C11/4076 ,  G11C2207/2281

    摘要： The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.

    Semiconductor integrated circuit device
    10.
    发明申请
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US20050162969A1

    公开(公告)日：2005-07-28

    申请号：US11040030

    申请日：2005-01-24

    申请人： Masatoshi Hasegawa ,  Shuichi Miyaoka

    发明人： Masatoshi Hasegawa ,  Shuichi Miyaoka

    IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/1069 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/12 ,  G11C11/4076 ,  G11C2207/2281

    摘要： The present invention provides a semiconductor integrated circuit device equipped with a memory circuit, which realizes speeding up of its operation in a simple configuration or realizes high reliability and enhancement of product yields in a simple configuration. A memory cell is selected from within a memory array having a plurality of memory cells by a selector or selection circuit. MOSFETs constituting a precharge circuit provided for signal lines for transferring a read signal therefrom to a main amplifier are respectively brought to an on state based on a memory cell select start signal transferred to the selection circuit and brought to an off state prior to the transfer of the read signal from the memory cell to thereby complete precharging, whereby NBTI degradation at standby is avoided.

    摘要翻译： 本发明提供一种配备有存储电路的半导体集成电路器件，其以简单的配置实现其操作的加速或者以简单的配置实现高可靠性和产品产量的提高。 通过选择器或选择电路从具有多个存储单元的存储器阵列内选择存储单元。 构成为将用于将读取信号传送到主放大器的信号线的预充电电路的MOSFET分别基于传送到选择电路的存储单元选择开始信号而变为导通状态，并且在转移 来自存储器单元的读取信号从而完成预充电，从而避免在待机时NBTI退化。