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102 条记录 (耗时 0.088 秒)

    Electric apparatus having heat radiating fin
    1.
    发明授权
    Electric apparatus having heat radiating fin 失效
    具有散热片的电器

    公开(公告)号：US5940272A

    公开(公告)日：1999-08-17

    申请号：US904862

    申请日：1997-08-01

    申请人： Akihiko Emori ,  Hiroyuki Hanei ,  Tsunehiro Endo ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama ,  Kazuo Kato

    发明人： Akihiko Emori ,  Hiroyuki Hanei ,  Tsunehiro Endo ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama ,  Kazuo Kato

    IPC分类号： H02B1/56 ,  H02M7/00 ,  H02M7/04 ,  H02M7/48 ,  H02P27/06 ,  H05K7/14 ,  H05K7/20

    CPC分类号： H05K7/20927 ,  H02M7/003 ,  H01L2924/1616

    摘要： An electric apparatus has a plurality of electric parts and a casing made of electrically conductive material for accommodating therein or mounting thereon a plurality of electric parts. The casing, which has a cavity therein, is provided with a plurality of projections for radiating heat generated by the electric parts in the cavity. The casing is provided with openings for allowing a heat conductive medium to flow into and out of the casing. Further, an electric apparatus has a plurality of electric parts and a casing made of electrically conductive material for accommodating therein or mounting thereon a plurality of electric parts. The casing is provided with openings for allowing a heat conductive medium to flow into and out of the casing. The casing is provided therein with a partition wall which is made of electrically conductive material for dividing the interior of the casing into a plurality of zones along a direction of a flow of the heat conductive medium.

    摘要翻译： 电气设备具有多个电气部件和由导电材料制成的壳体，用于容纳其中或安装有多个电气部件。 在其中具有空腔的壳体设置有用于散发由腔中的电气部件产生的热量的多个突起。 壳体设置有用于允许导热介质流入和流出壳体的开口。 此外，电气设备具有多个电气部件和由导电材料制成的壳体，用于容纳其中或安装有多个电气部件。 壳体设置有用于允许导热介质流入和流出壳体的开口。 壳体设置有分隔壁，该分隔壁由导电材料制成，用于将壳体的内部沿着导热介质的流动方向分成多个区域。

    Semiconductor memory device and sense circuit
    2.
    发明授权
    Semiconductor memory device and sense circuit 失效
    半导体存储器件和感测电路

    公开(公告)号：US5734616A

    公开(公告)日：1998-03-31

    申请号：US694059

    申请日：1996-08-08

    申请人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

    发明人： Hideto Kazama ,  Shuichi Miyaoka ,  Akihiko Emori ,  Kinya Mitsumoto ,  Tomoyuki Someya ,  Masahiro Iwamura ,  Noboru Akiyama

    IPC分类号： G11C11/419 ,  G11C7/00

    CPC分类号： G11C11/419

    摘要： A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.

    摘要翻译： 静态RAM包括前置放大器，其仅由具有其电源电压的集电极的射极跟随器晶体管组成，与通过列开关连接到互补数据线的子公共数据线对一一对应 成对的存储器阵列。 前置放大器设置有在选择状态期间导通的第一开关，以将子公共数据线对连接到晶体管的基极;以及第二开关，其在未选择状态期间导通，以向基极提供一定的偏置 电压低于副公共数据线对上的读出信号电压。 射极跟随器晶体管的发射极共同连接形成共同的发射极线，其连接到由CMOS晶体管构成的主放大器的输入端对。

    Synchronous memory with pipelined write operation
    3.
    发明授权
    Synchronous memory with pipelined write operation 失效
    具有流水线写入操作的同步存储器

    公开(公告)号：US5761150A

    公开(公告)日：1998-06-02

    申请号：US651873

    申请日：1996-05-21

    申请人： Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    发明人： Seigoh Yukutake ,  Kinya Mitsumoto ,  Takashi Akioka ,  Masahiro Iwamura ,  Noboru Akiyama

    IPC分类号： G11C11/413 ,  G06F12/00 ,  G11C7/10 ,  G11C8/06 ,  G11C11/401 ,  G11C11/407 ,  G11C11/418 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C8/06 ,  G11C11/418 ,  G11C7/1072 ,  G11C2207/2218

    摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.

    摘要翻译： 提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。 为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。 中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。 选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。

    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels
    6.
    发明授权
    Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效
    用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作

    公开(公告)号：US5646897A

    公开(公告)日：1997-07-08

    申请号：US426384

    申请日：1995-04-21

    申请人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    发明人： Seigou Yukutake ,  Masahiro Iwamura ,  Kinya Mitsumoto ,  Takashi Akioka ,  Noboru Akiyama

    IPC分类号： G11C7/10 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

    CPC分类号： G11C29/028 ,  G11C29/50 ,  G11C7/1051 ,  G11C11/41 ,  G11C2029/5004 ,  G11C29/34

    摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.

    摘要翻译： 提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。 该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用 双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。 还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平 元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。

    Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device
    8.
    发明授权
    Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device 失效
    双极晶体管MOS晶体管混合半导体集成电路器件

    公开(公告)号：US5378941A

    公开(公告)日：1995-01-03

    申请号：US983467

    申请日：1992-11-30

    申请人： Yoji Nishio ,  Ikuro Masuda ,  Kazuo Kato ,  Shigeo Kuboki ,  Masahiro Iwamura

    发明人： Yoji Nishio ,  Ikuro Masuda ,  Kazuo Kato ,  Shigeo Kuboki ,  Masahiro Iwamura

    IPC分类号： H03K19/08 ,  H01L21/331 ,  H01L21/82 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/73 ,  H03K19/173 ,  H03K19/02 ,  H03K19/084

    CPC分类号： H01L27/11896

    摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.

    摘要翻译： 高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个 输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。 每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。