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公开(公告)号：US5734616A
公开(公告)日：1998-03-31
申请号：US694059
申请日：1996-08-08
申请人： Hideto Kazama , Shuichi Miyaoka , Akihiko Emori , Kinya Mitsumoto , Tomoyuki Someya , Masahiro Iwamura , Noboru Akiyama
发明人： Hideto Kazama , Shuichi Miyaoka , Akihiko Emori , Kinya Mitsumoto , Tomoyuki Someya , Masahiro Iwamura , Noboru Akiyama
IPC分类号： G11C11/419 , G11C7/00
CPC分类号： G11C11/419
摘要： A static RAM includes pre-amplifiers, which are made up solely of emitter-follower transistors having their collectors supplied with the power voltage, in one-to-one correspondence to sub common data line pairs which are connected by column switches to complementary data line pairs of memory arrays. The pre-amplifier is provided with a first switch which turns on during the selected state to connect the sub common data line pair to the bases of the transistors and a second switch which turns on during the unselected state to provide the bases with a certain bias voltage lower than the readout signal voltage on the sub common data line pair. The emitter-follower transistors have their emitters connected commonly to form common emitter lines, which are connected to pairs of input terminals of main amplifiers made up of CMOS transistors.
摘要翻译： 静态RAM包括前置放大器，其仅由具有其电源电压的集电极的射极跟随器晶体管组成，与通过列开关连接到互补数据线的子公共数据线对一一对应 成对的存储器阵列。 前置放大器设置有在选择状态期间导通的第一开关，以将子公共数据线对连接到晶体管的基极;以及第二开关，其在未选择状态期间导通，以向基极提供一定的偏置 电压低于副公共数据线对上的读出信号电压。 射极跟随器晶体管的发射极共同连接形成共同的发射极线，其连接到由CMOS晶体管构成的主放大器的输入端对。
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公开(公告)号：US5638335A
公开(公告)日：1997-06-10
申请号：US649166
申请日：1996-05-17
申请人： Noboru Akiyama , Seigoh Yukutake , Sadayuki Ohkuma , Akihiko Emori , Takashi Akioka , Shuichi Miyaoka , Shinji Nakazato , Kinya Mitsumoto
发明人： Noboru Akiyama , Seigoh Yukutake , Sadayuki Ohkuma , Akihiko Emori , Takashi Akioka , Shuichi Miyaoka , Shinji Nakazato , Kinya Mitsumoto
CPC分类号： G11C5/06 , G11C7/062 , G11C7/1048 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096
摘要： A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.
摘要翻译： 一种存储器件，包括具有多个位的存储器阵列，包括奇偶校验位，并且包括多个存储器块，以及位结构改变部分，用于改变存储器阵列的输入/输出位，其中存储器块的数量 被规定为3的整数倍，并且多个存储块的输入/输出位是偶数。 因此，可以改变具有奇偶校验位并且能够将输入/输出位改变为多个位结构的半导体存储器的位结构，同时保持存储器块的位结构并且不增加传播延迟 时间。
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3.发明授权Logic gate circuit and parallel bit test circuit for semiconductor memory devices, capable of operation at low power source levels 失效用于半导体存储器件的逻辑门电路和并行位测试电路，能够在低电源电平下工作
公开(公告)号：US5646897A
公开(公告)日：1997-07-08
申请号：US426384
申请日：1995-04-21
CPC分类号： G11C29/028 , G11C29/50 , G11C7/1051 , G11C11/41 , G11C2029/5004 , G11C29/34
摘要： A logic circuit is provided for a memory device which can be operated at a high speed with a lower voltage power source level than conventional devices. This logic circuit can be used in a multi-bit test circuit executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, receiving the output of the wired-OR-logic operation by an emitter follower using a bipolar transistor, and outputting an AND signal of the complementary logic signals by a level comparing circuit. A sense amplifier is also provided for executing the wired-OR-logic operation of complementary logic signals from a plurality of pre-sense amplifiers, raising the level of the output of the wired-OR-logic operation by a level shift circuit having a semiconductor element for applying an inverse bias potential to an input signal, executing the wired-OR-operation of the shifted up output and outputs from other blocks, and receiving and amplifying the output of the wired-OR-logic operation.
摘要翻译： 提供了一种用于存储器件的逻辑电路，其可以以比传统器件更低的电压电源电平在高速下操作。 该逻辑电路可以用于执行来自多个预读取放大器的互补逻辑信号的有线或逻辑运算的多位测试电路，通过射极跟随器接收有线或逻辑运算的输出，使用 双极晶体管，并通过电平比较电路输出互补逻辑信号的“与”信号。 还提供读出放大器，用于执行来自多个预读放大器的互补逻辑信号的有线或逻辑运算，通过具有半导体的电平移位电路提高布线或逻辑运算的输出电平 元件，用于对输入信号施加反向偏置电位，执行移位上升输出的线或运算和其他块的输出，以及接收和放大有线逻辑运算的输出。
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公开(公告)号：US5761150A
公开(公告)日：1998-06-02
申请号：US651873
申请日：1996-05-21
IPC分类号： G11C11/413 , G06F12/00 , G11C7/10 , G11C8/06 , G11C11/401 , G11C11/407 , G11C11/418 , G11C8/00 , G11C7/00
CPC分类号： G11C8/06 , G11C11/418 , G11C7/1072 , G11C2207/2218
摘要： There is provided a method of controlling an internal address signal of an RAM in which a late-write method is realized on a chip. Two sets of address registers for reading and writing are provided for each address and further a middle register is provided between the two sets of address registers. The middle register is controlled by a signal formed by obtaining the AND result of a clock signal and a write enable signal and the two sets of address registers for reading and writing are controlled only by the clock signal. A selection circuit selects outputs of the two sets of address registers as an input in accordance with the write enable signal to control an internal address.
摘要翻译： 提供了一种控制RAM的内部地址信号的方法，其中在芯片上实现了后期写入方法。 为每个地址提供两组用于读取和写入的地址寄存器，并且还在两组地址寄存器之间提供中间寄存器。 中间寄存器由通过获得时钟信号和写入使能信号的AND结果而形成的信号控制，并且用于读取和写入的两组地址寄存器仅由时钟信号控制。 选择电路根据写使能信号选择两组地址寄存器的输出作为输入，以控制内部地址。
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5.发明授权High-speed semiconductor memory device and data processing system using the same 失效高速半导体存储器件和数据处理系统使用相同
公开(公告)号：US5654931A
公开(公告)日：1997-08-05
申请号：US213531
申请日：1994-03-16
申请人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
发明人： Akihiro Tamba , Masahiro Iwamura , Yutaka Kobayashi , Kinya Mitsumoto , Tatsumi Yamauchi , Shuko Yamauchi , Takashi Akioka
CPC分类号： G11C7/22
摘要： A semiconductor integrated circuit device is divided into a plurality of blocks, which are individually equipped with signal generate units such that the signal generate units are distributed in the semiconductor integrated circuit device. The semiconductor integrated circuit device is preferably constructed to generate the pulse signal by the pulse generate units which are provided for the individual blocks, after all initial logic operations on the data and control signals have been taken. Thanks to this construction, an SRAM, for example, can have its write recovery time minimized to 0 so that it can achieve high-speed operations. Moreover, since predecoders are provided for the individual blocks, the wiring line number and area in the chip can be reduced to improve the degree of integration of the semiconductor integrated circuit device. Still moreover, signal delay and skew can be reduced in the chip so that high-speed can be achieved. Another feature is that either the input/output pads of the data into or out of the semiconductor integrated circuit device or their accompanying circuit units are distributed in the semiconductor integrated circuit device. The individual features described above can be used solely or in combination, if necessary, to achieve the above-specified objects.
摘要翻译： 半导体集成电路器件被分成多个块，它们分别配备有信号生成单元，使得信号生成单元分布在半导体集成电路器件中。 优选地，半导体集成电路器件被构造为在对数据和控制信号进行了所有初始逻辑运算之后，通过针对各个块提供的脉冲产生单元产生脉冲信号。 由于这种结构，例如，SRAM可以将其写恢复时间最小化为0，从而可以实现高速操作。 此外，由于为每个块提供预编码器，所以可以减少芯片中的布线数量和面积，以提高半导体集成电路器件的集成度。 此外，芯片中的信号延迟和偏斜可以降低，从而可以实现高速度。 另一个特征是将半导体集成电路器件的数据的输入/输出焊盘或其相应的电路单元分布在半导体集成电路器件中。 如果需要，可以单独地或组合地使用上述各个特征来实现上述目的。
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公开(公告)号：US5392246A
公开(公告)日：1995-02-21
申请号：US205161
申请日：1994-03-03
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04 , G11C29/24 , G11L7/00
CPC分类号： G11C29/804 , G11C29/24 , G11C29/808
摘要： An area of a semiconductor chip, on which a memory is disposed, is divided into a plurality of memory blocks and redundant memory blocks, each memory block is divided into a plurality of unit arrays of columns for replacing, each redundant memory block is divided into a plurality of unit arrays of redundant columns, a plurality of memory cells are disposed in each unit array of columns for replacing and each unit array of redundant columns, a memory cell group in each unit array of columns for replacing is connected to a word line and a data line, a redundant memory cell group of each unit array of redundant columns is connected to a redundant word line and a redundant data line, a first data selection circuit for controlling data selection with respect to the unit array of redundant columns is disposed in each memory block, a second data selection circuit for controlling data selecting with respect to the unit array group of redundant columns is disposed in each redundant memory block, and a third data selection circuit for selecting and transmitting only data selected either of the data selection circuit is disposed, wherein, if each memory block has no defect, data selected by the first data selection circuit, that is, data selected from the unit array of columns for replacing of each memory block is transmitted as it is by way of the third data selection circuit, if any one of the memory blocks has a defect, data selection with respect to the unit array of columns for replacing that has encountered the defect is inhibited, the unit array of redundant columns of the redundant memory block is instructed in place of the unit array of columns for replacing that has encountered the defect, and data is, by the second data selection circuit, selected from the selected unit array of redundant columns in place of the replacement unit array that has encountered the defect as to transmit the selected data by way of the third data selection circuit.
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公开(公告)号：US07623397B2
公开(公告)日：2009-11-24
申请号：US11514101
申请日：2006-09-01
申请人： Noriyuki Itano , Kinya Mitsumoto
发明人： Noriyuki Itano , Kinya Mitsumoto
CPC分类号： H03L7/0812 , G06F1/04 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C7/222 , H01L2224/04105 , H01L2224/12105 , H01L2224/20
摘要： A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
摘要翻译： 一种具有与其中的半导体芯片连接的封装电路部分的半导体器件。 半导体芯片包括多个焊盘电极，封装电路部分包括连接到半导体芯片上的焊盘电极的布线，安装端子，以及用于接收从预定的一个焊盘电极输出的信号的第一信号路径， 信号到另一个焊盘电极。 第一信号路径包括延迟元件，该延迟元件与从安装端子中的预定安装端子到另一个安装端子延伸穿过半导体芯片的第二信号路径中的延迟相比较，并且设置在用于相位比较的反馈路径上用于使 从第二信号路径到输入信号到第二信号路径的相位的输出信号的相位。
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公开(公告)号：US07068551B2
公开(公告)日：2006-06-27
申请号：US11046690
申请日：2005-02-01
IPC分类号： G11C7/00
CPC分类号： G11C5/063 , G11C7/02 , G11C7/1048 , G11C7/18 , G11C11/419 , H01L27/11
摘要： Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
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公开(公告)号：US5631600A
公开(公告)日：1997-05-20
申请号：US361722
申请日：1994-12-23
CPC分类号： G05F3/267
摘要： A constant current generating circuit is provided with a first current generating circuit unit which generates a first current having a positive temperature dependency and includes a pair of first and second bipolar transistors, a first current mirror circuit comprised of a plurality of first MOS transistors which regulates a current density ratio of the currents fed to the first and second bipolar transistors to be constant and derives the first current and a first circuit disposed between the first and second bipolar transistors and the first current mirror circuit for limiting dependency of the currents flowing through the first and second bipolar transistors on a voltage of a power source applied to the first current mirror circuit, a second current generating circuit unit is also provided which generates a second current having as negative temperature dependency and which includes a third bipolar transistor and a second resistor through which the second current is derived. Also, a summing current generating circuit unit is provided which sums the first current and the second current and generates a constant current with substantially no temperature dependency representing the summed current. This summary current generating circuit unit includes a second current mirror circuit comprised of a plurality of second MOS transistors which generates the constant current representing the summed current.
摘要翻译： 恒定电流产生电路具有产生具有正温度依赖性的第一电流并包括一对第一和第二双极晶体管的第一电流产生电路单元，由多个第一MOS晶体管组成的第一电流镜电路，第一MOS晶体管调节 馈送到第一和第二双极晶体管的电流的电流密度比恒定并导出第一电流，以及设置在第一和第二双极晶体管与第一电流镜电路之间的第一电路，用于限制流经 在施加到第一电流镜电路的电源的电压上的第一和第二双极晶体管，还提供产生具有负温度依赖性的第二电流的第二电流产生电路单元，并且包括第三双极晶体管和第二电阻 通过其导出第二电流。 此外，提供了一个求和电流产生电路单元，其将第一电流和第二电流相加，并产生一个恒定电流，基本上没有表示总和电流的温度依赖性。 该汇总电流产生电路单元包括由多个第二MOS晶体管组成的第二电流镜电路，该第二MOS晶体管产生表示总和电流的恒定电流。
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公开(公告)号：US5392250A
公开(公告)日：1995-02-21
申请号：US5219
申请日：1993-01-15
IPC分类号： G11C11/417 , G11C11/409 , G11C11/419 , H01L21/8244 , H01L27/11 , G11C7/00 , G11C11/40
CPC分类号： G11C11/419 , H01L27/11
摘要： In a semiconductor memory device of the present invention, data read from a memory cell to a pair of complementary data lines or a pair of common data lines are fed directly to an output circuit not through any sense amplifier. As a result, the delay time of the sense amplifier itself is omitted from the address access time of the conventional semiconductor memory device using the sense amplifier, so that the semi-conductor memory device of the present invention can have its address access time made shorter than that of the conventional semiconductor memory device.
摘要翻译： 在本发明的半导体存储器件中，从存储单元读取到一对互补数据线或一对公共数据线的数据直接通过任何读出放大器直接馈送到输出电路。 结果，使用读出放大器的传统半导体存储器件的地址访问时间省略了读出放大器本身的延迟时间，使得本发明的半导体存储器件可以使其地址访问时间缩短 比传统的半导体存储器件。
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