公开(公告)号：US20120212273A1

公开(公告)日：2012-08-23

申请号：US13029949

申请日：2011-02-17

申请人： Nhon Nguyen ,  Phat Truong ,  John Phan

发明人： Nhon Nguyen ,  Phat Truong ,  John Phan

IPC分类号： H03H11/26 ,  H03K3/00

CPC分类号： G11C7/222 ,  H03L7/0814 ,  H03L7/0816

摘要： A synchronous signal generating circuit. The synchronous signal generating circuit includes a delay locked loop (DLL), an emulator and a multiplexer. The DLL is operative to delay a reference clock signal according to a count value to generate a first output clock signal. The count value is generated according to phase difference between the first output clock signal and the reference clock signal. The emulator is operative to provide a function of the DLL and includes a programmable delay line which is operative to receive the reference clock signal and a reference count value, wherein the reference clock signal is delayed according to the reference count value to generate a second output clock signal. The multiplexer is operative to receive the first and second output clock signal and selectively output the first or second output clock signal. The first output clock signal is outputted in a first mode and the second output clock signal is outputted in a second mode.

摘要翻译： 同步信号发生电路。 同步信号发生电路包括延迟锁定环（DLL），仿真器和复用器。 DLL用于根据计数值延迟参考时钟信号以产生第一输出时钟信号。 计数值根据第一输出时钟信号和参考时钟信号之间的相位差产生。 仿真器可操作以提供DLL的功能，并且包括可操作以接收参考时钟信号和参考计数值的可编程延迟线，其中参考时钟信号根据参考计数值被延迟以产生第二输出 时钟信号。 多路复用器可操作以接收第一和第二输出时钟信号并选择性地输出第一或第二输出时钟信号。 第一输出时钟信号以第一模式输出，第二输出时钟信号以第二模式输出。

公开(公告)号：US08369165B2

公开(公告)日：2013-02-05

申请号：US13029949

申请日：2011-02-17

申请人： Nhon Nguyen ,  Phat Truong ,  John Phan

发明人： Nhon Nguyen ,  Phat Truong ,  John Phan

IPC分类号： G11C7/00

CPC分类号： G11C7/222 ,  H03L7/0814 ,  H03L7/0816

摘要： A synchronous signal generating circuit. The synchronous signal generating circuit includes a delay locked loop (DLL), an emulator and a multiplexer. The DLL is operative to delay a reference clock signal according to a count value to generate a first output clock signal. The count value is generated according to phase difference between the first output clock signal and the reference clock signal. The emulator is operative to provide a function of the DLL and includes a programmable delay line which is operative to receive the reference clock signal and a reference count value, wherein the reference clock signal is delayed according to the reference count value to generate a second output clock signal. The multiplexer is operative to receive the first and second output clock signal and selectively output the first or second output clock signal. The first output clock signal is outputted in a first mode and the second output clock signal is outputted in a second mode.

摘要翻译： 同步信号发生电路。 同步信号发生电路包括延迟锁定环（DLL），仿真器和复用器。 DLL用于根据计数值延迟参考时钟信号以产生第一输出时钟信号。 计数值根据第一输出时钟信号和参考时钟信号之间的相位差产生。 仿真器可操作以提供DLL的功能，并且包括可操作以接收参考时钟信号和参考计数值的可编程延迟线，其中参考时钟信号根据参考计数值被延迟以产生第二输出 时钟信号。 多路复用器可操作以接收第一和第二输出时钟信号并选择性地输出第一或第二输出时钟信号。 第一输出时钟信号以第一模式输出，第二输出时钟信号以第二模式输出。

公开(公告)号：US07911262B2

公开(公告)日：2011-03-22

申请号：US12413596

申请日：2009-03-29

申请人： Phat Truong ,  Pauline Mai ,  Chia-Jen Chang

发明人： Phat Truong ,  Pauline Mai ,  Chia-Jen Chang

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H03K19/00384

摘要： An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit.

摘要翻译： 集成电路包括：预驱动器级，耦合到外部电源电压，用于控制最终的驱动级; 耦合到预驱动器级和外部电源电压的最终驱动器级，用于提供输出电压; 耦合到预驱动器级的补偿电路，用于向前驱动器级提供偏置电压，其补偿外部电源电压的变化，以控制通过前驱动器级的电流; 以及耦合到外部电源电压和补偿电路的偏置电路，用于提供偏置电压作为对补偿电路的输入。

公开(公告)号：US07737728B1

公开(公告)日：2010-06-15

申请号：US12413603

申请日：2009-03-30

申请人： Phat Truong ,  Pauline Mai

发明人： Phat Truong ,  Pauline Mai

IPC分类号： H03K19/094

CPC分类号： H03K17/164 ,  H03K19/00361 ,  H03K19/00369

摘要： An off-chip driver (OCD) includes: a logic circuit, for providing a logic signal input; a pre-driver stage, coupled to the logic circuit, for providing a ramped up voltage in response to the logic signal input; a final driver stage, coupled to the pre-driver stage, for providing an output voltage in response to the ramped up voltage; and a bias circuit, coupled to the pre-driver stage, for providing a constant bias voltage to the pre-driver stage, wherein the constant bias voltage keeps the pre-driver stage within an operational range to compensate for variations in process, temperature and supply voltage.

摘要翻译： 片外驱动器（OCD）包括：用于提供逻辑信号输入的逻辑电路; 耦合到所述逻辑电路的预驱动器级，用于响应于所述逻辑信号输入而提供斜升电压; 耦合到预驱动器级的最终驱动器级，用于响应于上升电压而提供输出电压; 以及耦合到所述预驱动器级的偏置电路，用于向所述预驱动器级提供恒定的偏置电压，其中所述恒定偏置电压将所述预驱动器级保持在操作范围内以补偿过程，温度和 电源电压。

公开(公告)号：US20090295466A1

公开(公告)日：2009-12-03

申请号：US12129683

申请日：2008-05-30

申请人： Phat Truong ,  Jon Nguyen

发明人： Phat Truong ,  Jon Nguyen

IPC分类号： G05F1/10

CPC分类号： G05F3/247

摘要： Controlled voltage circuit for compensating the performance variations in integrate circuits caused by voltage supply, temperature, and process variations is proposed. The controlled voltage circuit includes several MOSFET transistors connected in series, a unity gain operational amplifier, and a constant current source with an input terminal and an output terminal. The input source terminal of the first MOSFET is connected to a constant current source and to the unity gain operational amplifier. The output terminal of the circuit is connected to the CMOS delay block. To compensate for the performance variation, the output voltage node at or before the unity gain operational amplifier is shifted higher as the operating process state is slowed down or as the temperature is increased. Conversely, the output voltage node is shifted lower as the process becomes faster or the temperature is reduced.

摘要翻译： 提出了用于补偿由电源，温度和工艺变化引起的集成电路性能变化的控制电压电路。 控制电压电路包括串联连接的几个MOSFET晶体管，单位增益运算放大器和具有输入端子和输出端子的恒流源。 第一MOSFET的输入源极端子连接到恒流源和单位增益运算放大器。 电路的输出端子连接到CMOS延迟块。 为了补偿性能变化，单位增益运算放大器之前或之前的输出电压节点随着运行过程状态变慢或温度升高而偏移。 相反，当过程变得更快或者温度降低时，输出电压节点移动较低。

公开(公告)号：US20090238014A1

公开(公告)日：2009-09-24

申请号：US12050950

申请日：2008-03-19

申请人： Chia-Jen Chang ,  Phat Truong

发明人： Chia-Jen Chang ,  Phat Truong

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C8/06 ,  G11C7/1072

摘要： A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.

摘要翻译： 一种用于动态地使同步存储器阵列中的地址接收器的方法包括：控制所有地址接收器最初处于关闭状态; 生成命令信号并产生地址信号; 延迟地址信号，使得在命令信号和地址信号之间存在延迟; 以及当所述同步存储器阵列接收到所述命令信号时，选择性地接通对应于所述地址信号的地址接收器。

公开(公告)号：US4820941A

公开(公告)日：1989-04-11

申请号：US150863

申请日：1988-02-01

申请人： Debra J. Dolby ,  John F. Schreck ,  Phat Truong

发明人： Debra J. Dolby ,  John F. Schreck ,  Phat Truong

IPC分类号： G11C17/00 ,  G11C8/00 ,  G11C8/10 ,  G11C16/06 ,  G11C16/08 ,  H03K17/10

CPC分类号： G11C16/08 ,  G11C8/10

摘要： A driver circuit for applying both read and program voltages to a wordline of an integrated-circuit memory-cell logic array. The driver circuit is comprised of a series driver transistor pair, of a driver enabling means for enabling and disenabling one of the transistors of the driver transistor pair, and of a latching means. The driver transistor used during read operation may be constructed with a relatively short source-drain channel, permitting faster access speed during read operation of the circuit.

公开(公告)号：US20110176376A1

公开(公告)日：2011-07-21

申请号：US13073991

申请日：2011-03-28

申请人： Chia-Jen Chang ,  Phat Truong

发明人： Chia-Jen Chang ,  Phat Truong

IPC分类号： G11C8/18

CPC分类号： G11C8/06 ,  G11C7/1072

摘要： A synchronous memory array includes: a command receiver, for receiving a command signal; an address receiver, for receiving an address signal corresponding to the command signal where the address signal is delayed with respect to the command signal and the address receiver is initially in an off state; and a decoder, coupled to the command receiver and the address receiver, for decoding the command signal to selectively generate a receiver enable signal for turning on the address receiver.

摘要翻译： 同步存储器阵列包括：命令接收器，用于接收命令信号; 地址接收器，用于接收对应于地址信号相对于命令信号延迟的命令信号的地址信号，并且地址接收器最初处于关闭状态; 以及耦合到命令接收器和地址接收器的解码器，用于对命令信号进行解码以选择性地产生用于接通地址接收器的接收器使能信号。

公开(公告)号：US20100244940A1

公开(公告)日：2010-09-30

申请号：US12413596

申请日：2009-03-29

申请人： Phat Truong ,  Pauline Mai ,  Chia-Jen Chang

发明人： Phat Truong ,  Pauline Mai ,  Chia-Jen Chang

IPC分类号： G05F5/02

CPC分类号： H03K19/00384

摘要： An integrated circuit includes: a pre-driver stage, coupled to an external supply voltage, for controlling the final driver stage; a final driver stage, coupled to the pre-driver stage and the external supply voltage, for providing an output voltage; a compensation circuit, coupled to the pre-driver stage, for providing a bias voltage to the pre-driver stage that compensates for variation in the external supply voltage, to control current through the pre-driver stage; and a bias circuit, coupled to the external supply voltage and the compensation circuit, for providing a bias voltage as an input to the compensation circuit.

摘要翻译： 集成电路包括：预驱动器级，耦合到外部电源电压，用于控制最终的驱动级; 耦合到预驱动器级和外部电源电压的最终驱动器级，用于提供输出电压; 耦合到预驱动器级的补偿电路，用于向前驱动器级提供偏置电压，其补偿外部电源电压的变化，以控制通过前驱动器级的电流; 以及耦合到外部电源电压和补偿电路的偏置电路，用于提供偏置电压作为对补偿电路的输入。

公开(公告)号：US20070226553A1

公开(公告)日：2007-09-27

申请号：US11385539

申请日：2006-03-21

申请人： Khaled Fekih-Romdhane ,  Phat Truong

发明人： Khaled Fekih-Romdhane ,  Phat Truong

IPC分类号： G11C29/00

CPC分类号： G11C29/26 ,  G11C29/40 ,  G11C2029/2602

摘要： Methods and apparatus that may be used to increase back-end testing throughput by allowing simultaneous access to multiple banks are provided. Techniques described herein take advantage of the compression that may be achieved in back-end testing, particularly when only an indication of whether a device has passed or failed is required and no indication of a particular location of a failure is necessary.

摘要翻译： 提供了可以通过允许同时访问多个存储体来增加后端测试吞吐量的方法和装置。 本文所描述的技术利用在后端测试中可以实现的压缩，特别是当仅需要设备通过或失败的指示时，并不需要指示故障的特定位置。