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    Contact plug and interconnect employing a barrier lining and a backfilled conductor material
    1.
    发明授权
    Contact plug and interconnect employing a barrier lining and a backfilled conductor material 失效
    使用阻挡衬里和回填导体材料的接触插头和互连

    公开(公告)号：US4884123A

    公开(公告)日：1989-11-28

    申请号：US16429

    申请日：1987-02-19

    申请人： Pankaj Dixit ,  Jack Sliwa ,  Richard K. Klein ,  Craig S. Sander ,  Mohammad Farnaam

    发明人： Pankaj Dixit ,  Jack Sliwa ,  Richard K. Klein ,  Craig S. Sander ,  Mohammad Farnaam

    IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768

    CPC分类号： H01L21/76846 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  Y10S257/915

    摘要： A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry. The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon. The contact of the invention avoids the problems of encroachment at the oxide-silicon interface and worm holes associated with other contact schemes but retains process simplicity.

    Contact plug and interconnect employing a barrier lining and a backfilled conductor material
    2.
    发明授权
    Contact plug and interconnect employing a barrier lining and a backfilled conductor material 失效
    使用阻挡衬里和回填导体材料的接触插头和互连

    公开(公告)号：US4960732A

    公开(公告)日：1990-10-02

    申请号：US436399

    申请日：1989-11-14

    申请人： Pankaj Dixit ,  Jack Sliwa ,  Richard K. Klein ,  Craig S. Sander ,  Mohammad Farnaam

    发明人： Pankaj Dixit ,  Jack Sliwa ,  Richard K. Klein ,  Craig S. Sander ,  Mohammad Farnaam

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

    摘要： A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion and contacting layer (18) of titanium formed along the walls of the insulating layer and in contact with the portion of the doped region; (b) a barrier layer (20) formed over the adhesion and contacting layer; and (c) a conductive material (22) formed over the barrier layer and at least substantially filling said contact hole. A patterned metal layer (26) forms an ohmic contact interconnect to other devices and external circuitry.The adhesion and contacting layer and barrier layer are either physically or chemically vapor deposited onto the oxide surface. The conductive layer comprises one of CVD or bias sputtered tungsten, molybdenum or in situ doped CVD polysilicon.The contact of the invention avoids the problems of encroachment at the oxide-silicon interface and worm holes associated with other contact schemes but retains process simplicity.

    摘要翻译： 在通过绝缘层（14）的接触孔（16）中形成稳定的低电阻接触，所述绝缘层（例如，二氧化硅）形成在半导体衬底（12）（例如硅）的表面上， 区域（10）。 触点包括（a）沿着绝缘层的壁形成并与掺杂区域的部分接触的钛的粘合和接触层（18）; （b）形成在粘附和接触层上的阻挡层（20）; 和（c）导电材料（22），其形成在所述阻挡层上并且至少基本上填充所述接触孔。 图案化金属层（26）与其它器件和外部电路形成欧姆接触互连。 粘附和接触层和阻挡层物理或化学气相沉积到氧化物表面上。 导电层包括CVD或偏置溅射的钨，钼或原位掺杂的CVD多晶硅中的一种。 本发明的接触避免了在与其它接触方案相关联的氧化物 - 硅界面和蠕虫孔上侵占的问题，但是保持了工艺简单性。

    High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism
    3.
    发明授权
    High speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism 失效
    高速互连系统，具有难治的非狗骨接触和主动的电迁移抑制机制

    公开(公告)号：US4847674A

    公开(公告)日：1989-07-11

    申请号：US24283

    申请日：1987-03-10

    申请人： Jack Sliwa ,  Mohammad Farnaam ,  Pankaj Dixit ,  Lewis N. Shen

    发明人： Jack Sliwa ,  Mohammad Farnaam ,  Pankaj Dixit ,  Lewis N. Shen

    IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532

    CPC分类号： H01L21/76886 ,  H01L23/532 ,  H01L2924/0002 ,  Y10S257/90 ,  Y10S257/915 ,  Y10T428/12576

    摘要： An interconnect (16', 18', 18"), whose interlevel contacts comprise refractory (10) to refractory or refractory to semiconductor substrate (13) interfaces, comprises patterned refractory core portions (10), consisting of tungsten or molybdenum, having top portions (10a) and opposed side portions (10b), provided with sidewall spacers (32a) of aluminum, gold or copper or alloys thereof and formed on surface (12a) of insulating layers (12). The sidewall spacers afford lateral low resistivity cladding of the refractory portions as well as suppression of the electromigration failure modes of voiding and whiskering, while leaving the top portion of the core portions available for refractory to refractory contacts and the bottom portion of the core portions available for refractory to refractory or refractory to silicon contacts. In this manner, an interconnect system is provided which has low electrical resistivity but which avoids the much poorer electromigration performance associated with aluminum to aluminum, aluminum to silicon, or aluminum to refractory contact-making as well as with industry-standard bilayer structures comprising refractory/aluminum for interconnect-making.

    Making a high speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism
    4.
    发明授权
    Making a high speed interconnect system with refractory non-dogbone contacts and an active electromigration suppression mechanism 失效
    制造具有难治性非狗骨接触的高速互连系统和有源电迁移抑制机制

    公开(公告)号：US4962060A

    公开(公告)日：1990-10-09

    申请号：US346050

    申请日：1989-05-02

    申请人： Jack Sliwa ,  Mohammad Farnaam ,  Pankaj Dixit ,  Lewis N. Shen

    发明人： Jack Sliwa ,  Mohammad Farnaam ,  Pankaj Dixit ,  Lewis N. Shen

    IPC分类号： H01L21/768 ,  H01L23/532

    CPC分类号： H01L23/532 ,  H01L21/76886 ,  H01L2924/0002 ,  Y10S438/927 ,  Y10T428/12743

    摘要： An interconnect (16',18', 18"), whose interlevel contacts comprise refractory (10) to refractory or refractory to semiconductor substrate (13) interfaces, comprises patterned refractory core portions (10), consisting of tungsten or molybdenum, having top portions (10a) and opposed side portions (10b), provided with sidewall spacers (32a) of aluminum, gold or copper or alloys thereof and formed on surfaces (12a) of insulating layers (12). The sidewall spacers afford lateral low resistivity cladding of the refractory portions as well as suppression of the electromigration failure modes of voiding and whiskering, while leaving the top portion of the core portions available for refractory to refractory contacts and the bottom portion of the core portions available for refractory to refractory or refractory to silicon contacts. In this manner, an interconnect system is provided which has low electrical resistivity but which avoids the much poorer electromigration performance associated with aluminum to aluminum, aluminum to silicon, or aluminum to refractory contact-making as well as with industry-standard bilayer structures comprising refractory/aluminum for interconnect-making.

    摘要翻译： 其互连（16'，18'，18“），其层间接触包括耐火材料（10），用于耐火材料或难以与半导体衬底（13）接口，包括由钨或钼组成的图案化的耐火芯部分（10），其具有 顶部（10a）和相对的侧部（10b），其设置有铝，金或铜的侧壁间隔件（32a）或其合金，并形成在绝缘层（12）的表面（12a）上。 侧壁间隔件提供了耐火部分的侧向低电阻率包层以及抑制空洞和晶须的电迁移失效模式，同时使芯部分的顶部部分可用于耐火接触点的耐火材料，并且芯部分的底部可用 用于难熔或难以与硅接触。 以这种方式，提供了一种互连系统，其具有低电阻率，但是避免了与铝，铝，铝或铝或耐火材料接触相关的更差的电迁移性能，以及包括耐火材料的工业标准双层结构 /铝用于互连。

    Avoiding spin-on-glass cracking in high aspect ratio cavities
    7.
    发明授权
    Avoiding spin-on-glass cracking in high aspect ratio cavities 失效
    避免在高纵横比的空腔中进行旋涂玻璃开裂

    公开(公告)号：US5119164A

    公开(公告)日：1992-06-02

    申请号：US652306

    申请日：1991-02-05

    申请人： John W. Sliwa, Jr. ,  Pankaj Dixit

    发明人： John W. Sliwa, Jr. ,  Pankaj Dixit

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/522 ,  H01L23/5329 ,  H01L2924/0002

    摘要： Before spin-on-glass (SOG) is applied and soft-cured over metal traces (10) having a height/width aspect ratio (of the spaces) of at least 1, the aluminum metal traces are selectively coated with selective tungsten (16). After SOG (18) is spun on and soft-cured, it is etched back to expose the metal interconnects. A selective tungsten wet etch in H.sub.2 O.sub.2 detaches the SOG from the metal walls, leaving silt-like voids (20). Stress-free SOG hard curing may now proceed. A capping layer (22) of SOG may now be applied, soft-cured, then hard-cured. Alternatively, other dielectric materials may be applied as the capping layer. Further, interfacial lateral sidewall voids (24) may be deliberately left unfilled, by employing a capping layer (24') of vapor-deposited oxide. The unfilled voids have a dielectric constant of 1.0, which is useful in extremely high speed devices. The resulting structure is comparatively stress-free as fabricated and is resistant to later environmentally-induced brittle tensile fracture.

    摘要翻译： 在旋涂玻璃（SOG）被施加并软化固化在具有至少1的高度/宽度纵横比（空间）的金属迹线（10）之后，铝金属迹线选择性地涂覆有选择性钨（16 ）。 在将SOG（18）纺丝并软化后，将其回蚀以暴露金属互连。 H 2 O 2中的选择性钨湿蚀刻将SOG从金属壁分离出来，留下淤泥状空隙（20）。 现在可以进行无压力的SOG硬化。 现在可以施加SOG的覆盖层（22），软化，然后硬化。 或者，可以施加其它电介质材料作为覆盖层。 此外，通过使用蒸镀氧化物的覆盖层（24'），界面侧壁侧壁空隙（24）可能故意留下未填充。 未填充的空隙的介电常数为1.0，这在非常高速的装置中是有用的。 所得到的结构在制造时是相对无应力的，并且耐受以后的环境诱导的脆性拉伸断裂。

    Process for avoiding spin-on-glass cracking in high aspect ratio cavities
    8.
    发明授权
    Process for avoiding spin-on-glass cracking in high aspect ratio cavities 失效
    避免在高纵横比腔中旋转玻璃裂纹的方法

    公开(公告)号：US5192715A

    公开(公告)日：1993-03-09

    申请号：US873920

    申请日：1992-04-24

    申请人： John W. Sliwa, Jr. ,  Pankaj Dixit

    发明人： John W. Sliwa, Jr. ,  Pankaj Dixit

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/522 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/902

    摘要： Before spin-on-glass (SOG) is applied and soft-cured over metal traces (10) having a height/width aspect ratio (of the spaces) of at least 1, the aluminum metal traces are selectively coated with selective tungsten (16). After SOG (18) is spun on and soft-cured, it is etched back to expose the metal interconnects. A selective tungsten wet etch in H.sub.2 O.sub.2 detaches the SOG from the metal walls, leaving silt-like voids (20). Stress-free SOG hard curing may now proceed. A capping layer (22) of SOG may now be applied, soft-cured, then hard-cured. Alternatively, other dielectric materials may be applied as the capping layer. Further, interfacial lateral sidewall voids (24) may be deliberately left unfilled, by employing a capping layer (22') of vapor-deposited oxide. The unfilled voids have a dielectric constant of 1.0, which is useful in extremely high speed devices. The resulting structure is comparatively stress-free as fabricated and is resistant to later environmentally-induced brittle tensile fracture.

    摘要翻译： 在旋涂玻璃（SOG）被施加并软化固化在具有至少1的高度/宽度纵横比（空间）的金属迹线（10）之后，铝金属迹线选择性地涂覆有选择性钨（16 ）。 在将SOG（18）纺丝并软化后，将其回蚀以暴露金属互连。 H 2 O 2中的选择性钨湿蚀刻将SOG从金属壁分离出来，留下淤泥状空隙（20）。 现在可以进行无压力的SOG硬化。 现在可以施加SOG的覆盖层（22），软化，然后硬化。 或者，可以施加其它电介质材料作为覆盖层。 此外，通过采用蒸镀氧化物的覆盖层（22'），界面侧向侧壁空隙（24）可有意留下未填充。 未填充的空隙的介电常数为1.0，这在非常高速的装置中是有用的。 所得到的结构在制造时是相对无应力的，并且耐受以后的环境诱导的脆性拉伸断裂。

    Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout
    9.
    发明授权
    Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout 有权
    用于在复杂的现有电路布局中有效定位和自动校正某些违规的方法和装置

    公开(公告)号：US07096447B1

    公开(公告)日：2006-08-22

    申请号：US10686471

    申请日：2003-10-15

    申请人： Mu-Jing Li ,  Suryanarayana R. Maturi ,  Pankaj Dixit

    发明人： Mu-Jing Li ,  Suryanarayana R. Maturi ,  Pankaj Dixit

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： An exemplary CAD design flow modifies an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair from bottom up to locate and correct isolated via rule violations by adding metal features and vias in a respective patch cell associated with each cluster cell. A large complex design is thus divided into cells so that multiple processes can work concurrently as if every process were working on the top level of the design layout.

    摘要翻译： 示例性CAD设计流程修改现有的大规模芯片布局以加强冗余通路设计规则以提高产量和可靠性。 每个金属通孔对从下往上运行，通过在与每个聚集单元相关联的相应补丁单元中添加金属特征和通孔来定位和校正隔离的规则违规。 因此，将大型复杂设计分为单元格，以便多个进程同时工作，就好像每个进程在设计布局的顶层工作一样。