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    Heterostructure transistor using real-space electron transfer
    1.
    发明授权
    Heterostructure transistor using real-space electron transfer 失效
    使用实时电子传输的异构结构晶体管

    公开(公告)号：US5055891A

    公开(公告)日：1991-10-08

    申请号：US532485

    申请日：1990-05-31

    Applicant: Nicolas J. Moll ,  Mark R. Hueschen ,  Marek E. Mierzwinski

    Inventor： Nicolas J. Moll ,  Mark R. Hueschen ,  Marek E. Mierzwinski

    IPC: H01L29/205 ,  H01L29/66 ,  H01L29/68 ,  H01L29/76

    CPC classification number: H01L29/7606

    Abstract: A charge injection transistor is a real-space electron transfer heterostructure with several novel features. The channel layer is comprised of In.sub.0.25 Ga.sub.0.75 As supported by a buffer layer of Al.sub.0.3 Ga.sub.0.7 As resting on the substrate. A barrier layer comprised of Al.sub.0.1 Ga.sub.0.9 As overlays the channel layer. Over this barrier is a layer of GaAs forming the electron drift region. The collector electrode is located on top of this drift layer, between the source and heater electrodes, which extend downward through the drift and barrier layers and create the electric field in the channel layer. Positive voltages are applied to the heater and collector, relative to the source. Electrons flow through the channel region and become heated. At sufficiently high temperature they escape over the barrier and travel through the drift region to the collector. In comparison with previous devices, the use of InGaAs in the channel layer provides a deeper quantum well for the conduction electrons, and suppresses leakage through the barrier at room temperatures. The collector drift layer has a short transit time delay. The location of the collector reduces parasitic leakage from the source, and the collector capacitance is small. These features enhance the high frequency performance of the device. The limiting power gain frequency and current gain frequency are at least twice the corresponding values attained in previous devices.

    System and method for controlling the size and/or distribution of catalyst nanoparticles for nanostructure growth
    2.
    发明申请
    System and method for controlling the size and/or distribution of catalyst nanoparticles for nanostructure growth 审中-公开
    用于控制纳米结构生长的催化剂纳米颗粒的尺寸和/或分布的系统和方法

    公开(公告)号：US20080032238A1

    公开(公告)日：2008-02-07

    申请号：US11229300

    申请日：2005-09-16

    Applicant: Jennifer Q. Lu ,  Nicolas J. Moll ,  Daniel B. Roitman ,  David T. Dutton

    Inventor： Jennifer Q. Lu ,  Nicolas J. Moll ,  Daniel B. Roitman ,  David T. Dutton

    IPC: B05D7/22 ,  G03C5/00

    CPC classification number: B01J35/0013 ,  B82Y30/00

    Abstract: Techniques for controlling the size and/or distribution of a catalyst nanoparticles on a substrate are provided. The catalyst nanoparticles comprise any species that can be used for growing a nanostructure, such as a nanotube, on the substrate surface. Polymers are used as a carrier of a catalyst payload, and such polymers self-assemble on a substrate thereby controlling the size and/or distribution of resulting catalyst nanoparticles. Amphiphilic block copolymers are known self-assembly systems, in which chemically-distinct blocks microphase-separate into a nanoscale morphology, such as cylindrical or spherical, depending on the polymer chemistry and molecular weight. Such block copolymers are used as a carrier of a catalyst payload, and their self-assembly into a nanoscale morphology controls size and/or distribution of resulting catalyst nanoparticles onto a substrate.

    Abstract translation: 提供了用于控制催化剂纳米颗粒在基材上的尺寸和/或分布的技术。 催化剂纳米颗粒包括可用于在衬底表面上生长纳米结构如纳米管的任何物质。 聚合物用作催化剂载体的载体，并且这样的聚合物自组装在基底上，从而控制所得催化剂纳米颗粒的尺寸和/或分布。 两亲性嵌段共聚物是已知的自组装体系，其中根据聚合物的化学性质和分子量，化学不同的嵌段微相分离成纳米尺度形态，例如圆柱形或球形。 这种嵌段共聚物用作催化剂载体的载体，并且它们自组装成纳米尺度形态控制所得催化剂纳米颗粒在基材上的尺寸和/或分布。

    Unipolar band minima devices
    3.
    发明授权
    Unipolar band minima devices 失效
    单极性带最小器件

    公开(公告)号：US5497012A

    公开(公告)日：1996-03-05

    申请号：US259808

    申请日：1994-06-15

    Applicant: Nicolas J. Moll

    Inventor： Nicolas J. Moll

    IPC: H01L29/205 ,  H01L29/861 ,  H01L31/0328 ,  H01L29/06 ,  H01L31/0336 ,  H01L31/072

    CPC classification number: H01L29/205 ,  H01L29/861

    Abstract: A semiconductor diode for providing a reduced recovery time at room temperature independent of any minority carrier recombination. The diode of the present invention comprises a first semiconductor material having a type of majority carriers and having a sub-band ordering associated with the majority carriers. The diode further comprises a second semiconductor material contacting the first material at a heterojunction, the second semiconductor material having the same type of majority carriers as the first semiconductor material and having a sub-band ordering associated with the majority carriers that is different from that of the first semiconductor material. It is theorized that the semiconductor diode of the present invention has a recovery time dependent upon scattering of carriers to various energy sub-bands within a heterojunction of the two different semiconductor materials. The diode of the present invention provides a reduced recovery time since a time of such scattering is extremely short.

    Abstract translation: 一种用于在室温下提供减少的恢复时间的半导体二极管，与任何少数载流子复合无关。 本发明的二极管包括具有多数载流子类型并具有与多数载流子相关联的子带排序的第一半导体材料。 二极管还包括在异质结接触第一材料的第二半导体材料，第二半导体材料具有与第一半导体材料相同类型的多数载流子，并且具有与多数载流子不同的多数载流子的子带排序 第一种半导体材料。 理论上，本发明的半导体二极管的恢复时间取决于载流子散射到两种不同半导体材料的异质结内的各种能量子带。 本发明的二极管提供了缩短的恢复时间，因为这种散射的时间非常短。

    Heterojunction semiconductor device having an intermediate layer for providing an improved junction
    6.
    发明授权
    Heterojunction semiconductor device having an intermediate layer for providing an improved junction 有权
    具有用于提供改善的结的中间层的异质结半导体器件

    公开(公告)号：US06822274B2

    公开(公告)日：2004-11-23

    申请号：US10358369

    申请日：2003-02-03

    Applicant: Sung Soo Yi ,  Nicolas J. Moll ,  Dave Bour ,  Hans G. Rohdin

    Inventor： Sung Soo Yi ,  Nicolas J. Moll ,  Dave Bour ,  Hans G. Rohdin

    IPC: H01L2906

    CPC classification number: H01L29/66318 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/7371

    Abstract: A heterojunction for a semiconductor device. The heterojunction has a first region formed from a first semiconductor material having a first conductivity type, a second region formed from a second semiconductor material having a second conductivity type, and an intermediate layer between the first region and the second region. The band line-up of the first region, the intermediate layer, and the second region has no bound states in its conduction band and no bound states in its valence band. The intermediate layer has a thickness small enough to allow electrons to tunnel from the first region to the second region with negligible attenuation. The semiconductor device may be a heterojunction bipolar transistor. The conduction band of the intermediate layer has a higher energy level than the conduction bands of the first and second regions.

    Abstract translation: 半导体器件的异质结。 异质结具有由具有第一导电类型的第一半导体材料形成的第一区域，由具有第二导电类型的第二半导体材料形成的第二区域，以及在第一区域和第二区域之间的中间层。 第一区域，中间层和第二区域的带阵列在其导带中没有结合状态，其价带中没有结合态。 中间层具有足够小的厚度，以允许电子以可忽略的衰减从第一区域隧穿到第二区域。 半导体器件可以是异质结双极晶体管。 中间层的导带具有比第一和第二区域的导带更高的能级。

    Heterojunction bipolar transistor (HBT) having improved emitter-base grading structure
    7.
    发明授权
    Heterojunction bipolar transistor (HBT) having improved emitter-base grading structure 失效
    具有改进的发射极基准分级结构的异质结双极晶体管（HBT）

    公开(公告)号：US06768141B2

    公开(公告)日：2004-07-27

    申请号：US10226771

    申请日：2002-08-23

    Applicant: Sandeep R. Bahl ,  Nicolas J. Moll ,  Mark Hueschen

    Inventor： Sandeep R. Bahl ,  Nicolas J. Moll ,  Mark Hueschen

    IPC: H01L31072

    CPC classification number: H01L29/7371 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/155

    Abstract: A heterojunction bipolar transistor (HBT), including an emitter formed from a first semiconductor material, a base formed from a second semiconductor material, and a grading structure between the emitter and the base is disclosed. The grading structure comprises a semiconductor material containing at least one element not present in the first and second semiconductor materials, where the grading structure has a conduction band energy substantially equal to a conduction band energy of the base at an interface between the base and the grading structure, and where the grading structure has a conduction band energy substantially equal to a conduction band energy of the emitter at an interface between the emitter and the grading structure.

    Abstract translation: 公开了一种异质结双极晶体管（HBT），包括由第一半导体材料形成的发射极，由第二半导体材料形成的基极以及发射极和基极之间的分级结构。 分级结构包括半导体材料，其含有不存在于第一和第二半导体材料中的至少一种元素，其中分级结构的导带能量基本上等于基底与基底与界面之间的界面处的导带能量 结构，并且其中分级结构的导带能量基本上等于发射器与分级结构之间的界面处的发射极的导带能量。

    System and method for planarizing a substrate surface having a non-planar surface topography
    8.
    发明授权
    System and method for planarizing a substrate surface having a non-planar surface topography 有权
    用于平坦化具有非平面表面形貌的衬底表面的系统和方法

    公开(公告)号：US06949008B1

    公开(公告)日：2005-09-27

    申请号：US10967973

    申请日：2004-10-19

    Applicant: Nicolas J. Moll ,  John Stephen Kofol ,  David Thomas Dutton

    Inventor： Nicolas J. Moll ,  John Stephen Kofol ,  David Thomas Dutton

    IPC: H01L21/00 ,  H01L21/3105

    CPC classification number: H01L21/31053 ,  Y10S438/942

    Abstract: A method for planarizing a substrate surface having a non-planar surface topography comprises forming a material layer over the substrate, the material layer having a surface topography, determining the surface topography of the material layer, and forming a mask using information relating to the surface topography of the material layer. The mask defines portions of averaging regions of the material layer for selective removal to equalize the averaging regions in average height, the averaging regions having a maximum dimension. The material layer is etched using the mask, and a planarizing layer is formed over the substrate surface. The planarizing layer provides a low-pass lateral filtering effect characterized by a length greater than the maximum dimension of the averaging region. The mask is created by determining the localized height of the material layer across a surface and using the mask to etch away corresponding portions of the material layer so that the average surface of the material layer approximates a planar surface. The surface of the second material layer is substantially planar. The system and method for planarizing a material layer provides for forming a substantially planar layer of material over a non-planar topography.

    Abstract translation: 用于平坦化具有非平面表面形貌的衬底表面的方法包括在衬底上形成材料层，材料层具有表面形貌，确定材料层的表面形貌，以及使用与表面相关的信息形成掩模 材料层的地形。 掩模定义材料层的平均区域的部分，用于选择性去除以平均平均高度的平均区域，平均区域具有最大尺寸。 使用掩模蚀刻材料层，并且在衬底表面上形成平坦化层。 平坦化层提供了一个特征在于长度大于平均区域的最大尺寸的低通横向滤波效应。 通过确定材料层跨越表面的局部高度并使用掩模蚀刻掉材料层的对应部分以使材料层的平均表面接近平坦表面来产生掩模。 第二材料层的表面基本上是平面的。 用于平坦化材料层的系统和方法提供了在非平面形貌上形成基本平坦的材料层。

    Band minima transistor
    9.
    发明授权
    Band minima transistor 失效
    带最小晶体管

    公开(公告)号：US5436469A

    公开(公告)日：1995-07-25

    申请号：US259801

    申请日：1994-06-15

    Applicant: Nicolas J. Moll

    Inventor： Nicolas J. Moll

    IPC: H01L29/76 ,  H01L29/205

    CPC classification number: H01L29/7606

    Abstract: A room temperature high speed transistor that does not suffer deleterious effects from plasmon scattering. The transistor of the present invention comprises a semiconducting base region having a type of majority carriers and sub-band ordering associated with the majority carriers. The transistor further comprises a semiconducting collector region contacting the base region at a collector-base heterojunction, the semiconducting collector region having the same type of majority carriers as the semiconducting base region and having a sub-band ordering different than that of the base region. The transistor further comprises a semiconducting emitter region contacting the base region at an emitter-base heterojunction, the semiconducting emitter region having the same type of majority carriers as the semiconducting base region. In active operation of the transistor of the present invention, carriers are injected from a main sub-band in the emitter region into a satellite sub-band the base region. The carriers are then transported from the satellite sub-band in the base region to a main sub-band in the collector region. Intravalley scattering processes, including plasmon scattering, are not deleterious in the present invention because the carriers injected into satellite sub-band of the base region are successful collected in the main sub-band of the collector region independent of any energy lost through the intravalley scattering.

    Abstract translation: 室温高速晶体管，不会受到等离子体激元散射的有害影响。 本发明的晶体管包括具有多数载流子类型的半导体基极区域和与多数载流子相关联的子带排序。 晶体管还包括在集电极 - 基极异质结处与基极区接触的半导体集电极区域，半导体集电极区域具有与半导体基极区域相同类型的多数载流子，并且具有与基极区域不同的子带排列。 所述晶体管还包括在发射极 - 基极异质结接触所述基极区的半导体发射极区，所述半导体发射极区具有与所述半导体基区相同类型的多数载流子。 在本发明的晶体管的有源操作中，载流子从发射极区域中的主子带注入基区的卫星子带。 载波然后从基区的卫星子带传送到集电区域的主子带。 包括等离子体激元散射在内的散射散射过程在本发明中不是有害的，因为注入基区域的卫星子带中的载流子成功地收集在集电极区域的主子带内，而与通过腔内散射损失的任何能量无关 。

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