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18 条记录 (耗时 0.024 秒)

    Method for integrating silicon-on-nothing devices with standard CMOS devices
    1.
    发明授权
    Method for integrating silicon-on-nothing devices with standard CMOS devices 有权
    将无硅器件与标准CMOS器件集成的方法

    公开(公告)号：US07906381B2

    公开(公告)日：2011-03-15

    申请号：US12167282

    申请日：2008-07-03

    申请人： Nicolas Loubet ,  Didier Dutartre ,  Stéphane Monfray

    发明人： Nicolas Loubet ,  Didier Dutartre ,  Stéphane Monfray

    IPC分类号： H01L21/84

    CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1207

    摘要： A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.

    摘要翻译： 提供了一种用于在单个衬底中制造第一和第二类型的晶体管的方法。 衬底的第一和第二活性区由横向隔离沟槽区限定，并且去除第二活性区的一部分，使得第二活性区位于第一活性区以下。 第一和第二层半导体材料形成在第二有源区上，使得第二层基本上处于与第一活性区相同的平面。 在第一活性区和第二层产生绝缘栅。 选择性地去除至少一个隔离沟槽区域，并且选择性地去除第一层，以便在第二层下形成隧道。 隧道填充有电介质材料以使第二层与衬底的第二活性区绝缘。 还提供了这种集成电路。

    Emission process for a single photon, corresponding semiconducting device and manufacturing process
    2.
    发明授权
    Emission process for a single photon, corresponding semiconducting device and manufacturing process 有权
    单光子发射过程，相应的半导体器件和制造工艺

    公开(公告)号：US06852993B2

    公开(公告)日：2005-02-08

    申请号：US10429908

    申请日：2003-05-05

    申请人： Stéphane Monfray ,  Didier Dutartre ,  Frédéric Boeuf

    发明人： Stéphane Monfray ,  Didier Dutartre ,  Frédéric Boeuf

    IPC分类号： H01S5/34 ,  H01L29/06 ,  H01L31/072 ,  H01L31/109

    CPC分类号： B82Y20/00 ,  H01S5/341 ,  H01S5/3412 ,  Y10S438/962

    摘要： An integrated circuit includes a semiconductor device forming a single photon source, and includes a MOS transistor on a silicon substrate. The MOS transistor has a mushroom shaped gate for outputting a single electron on its drain in a controlled manner in response to a control voltage applied to its gate. The transistor also includes at least one silicon compatible quantum box. The quantum box is electrically coupled to the drain region of the transistor, and is capable of outputting a single photon on reception of a single electron emitted by the transistor.

    摘要翻译： 集成电路包括形成单个光子源的半导体器件，并且在硅衬底上包括MOS晶体管。 MOS晶体管具有蘑菇形栅极，用于响应于施加到其栅极的控制电压以受控的方式在其漏极上输出单个电子。 晶体管还包括至少一个硅兼容的量子盒。 量子盒电耦合到晶体管的漏极区域，并且能够在接收由晶体管发射的单个电子器件时输出单个光子。

    Electrical energy generation device
    5.
    发明授权
    Electrical energy generation device 有权
    电能发电装置

    公开(公告)号：US08693165B2

    公开(公告)日：2014-04-08

    申请号：US13332124

    申请日：2011-12-20

    申请人： Thomas Skotnicki ,  Stéphane Monfray

    发明人： Thomas Skotnicki ,  Stéphane Monfray

    IPC分类号： H01G4/38 ,  H01G9/00 ,  H01G2/08

    CPC分类号： H01G9/0003 ,  H01G2/08 ,  H01G9/155 ,  H01L37/02

    摘要： A device for generating electrical energy from the heat dissipated by a heat source, comprising: a capacitor comprising two electrodes between which a ferroelectric material is present, said capacitor being arranged so as to be positioned to capture all or part of the heat dissipated by said heat source; a capacitive element a first electrode of which is connected to a first electrode of said capacitor; a recovery circuit interposed between the second electrode of said capacitor and the second electrode of the capacitive element, and able to have the current flowing between said second electrodes pass through it. a mechanism adapted to move the capacitor with respect to the heat source, said mechanism having at least one arm able to move between two positions, the capacitor being closer to the heat source in one of the two positions.

    摘要翻译： 一种用于从由热源消散的热量产生电能的装置，包括：电容器，包括两个电极，所述两个电极之间存在铁电材料，所述电容器被布置成被定位成捕获由所述 热源; 电容元件，其第一电极连接到所述电容器的第一电极; 插入在所述电容器的第二电极和电容元件的第二电极之间并且能够使在所述第二电极之间流动的电流通过其的恢复电路。 适于相对于所述热源移动所述电容器的机构，所述机构具有能够在两个位置之间移动的至少一个臂，所述电容器在所述两个位置中的一个位置更靠近所述热源。

    ELECTRICAL ENERGY GENERATION DEVICE
    6.
    发明申请
    ELECTRICAL ENERGY GENERATION DEVICE 有权
    电能发电装置

    公开(公告)号：US20120153905A1

    公开(公告)日：2012-06-21

    申请号：US13332124

    申请日：2011-12-20

    申请人： Thomas Skotnicki ,  Stéphane Monfray

    发明人： Thomas Skotnicki ,  Stéphane Monfray

    IPC分类号： H02N1/00

    CPC分类号： H01G9/0003 ,  H01G2/08 ,  H01G9/155 ,  H01L37/02

    摘要： A device for generating electrical energy from the heat dissipated by a heat source, comprising: a capacitor comprising two electrodes between which a ferroelectric material is present, said capacitor being arranged so as to be positioned to capture all or part of the heat dissipated by said heat source; a capacitive element a first electrode of which is connected to a first electrode of said capacitor; a recovery circuit interposed between the second electrode of said capacitor and the second electrode of the capacitive element, and able to have the current flowing between said second electrodes pass through it. a mechanism adapted to move the capacitor with respect to the heat source, said mechanism having at least one arm able to move between two positions, the capacitor being closer to the heat source in one of the two positions.

    摘要翻译： 一种用于从由热源消散的热量产生电能的装置，包括：电容器，包括两个电极，所述两个电极之间存在铁电材料，所述电容器被布置成被定位成捕获由所述 热源; 电容元件，其第一电极连接到所述电容器的第一电极; 插入在所述电容器的第二电极和电容元件的第二电极之间并且能够使在所述第二电极之间流动的电流通过其的恢复电路。 适于相对于所述热源移动所述电容器的机构，所述机构具有能够在两个位置之间移动的至少一个臂，所述电容器在所述两个位置中的一个位置更靠近所述热源。

    METHOD FOR MANUFACTURING A SUSPENDED MEMBRANE AND DUAL-GATE MOS TRANSISTOR
    7.
    发明申请
    METHOD FOR MANUFACTURING A SUSPENDED MEMBRANE AND DUAL-GATE MOS TRANSISTOR 有权
    制造悬浮膜和双栅极MOS晶体管的方法

    公开(公告)号：US20110121391A1

    公开(公告)日：2011-05-26

    申请号：US12949286

    申请日：2010-11-18

    申请人： Stéphane Monfray ,  Thomas Skotnicki

    发明人： Stéphane Monfray ,  Thomas Skotnicki

    IPC分类号： H01L29/786 ,  H01L21/762

    CPC分类号： H01L29/786 ,  H01L29/78648

    摘要： A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.

    摘要翻译： 一种用于制造单晶半导体衬底中的悬浮膜的方法，包括以下步骤：在衬底中形成限定有源区的绝缘环，从有源区去除材料，在有源区中依次形成第一和第二 层，所述第二层是单晶半导体层，将所述环的内周的一部分蚀刻到大于所述第二层的厚度的深度，去除所述第一层，使得所述第二层形成悬浮膜 在绝缘环中。

    Process for fabricating a heterostructure-channel insulated-gate field-effect transistor, and the corresponding transistor
    8.
    发明授权
    Process for fabricating a heterostructure-channel insulated-gate field-effect transistor, and the corresponding transistor 有权
    用于制造异质结构通道绝缘栅场效应晶体管的工艺及相应的晶体管

    公开(公告)号：US07436005B2

    公开(公告)日：2008-10-14

    申请号：US11227681

    申请日：2005-09-15

    申请人： Stéphane Monfray ,  Stéphan Borel ,  Thomas Skotnicki

    发明人： Stéphane Monfray ,  Stéphan Borel ,  Thomas Skotnicki

    IPC分类号： H01L29/94

    CPC分类号： H01L29/1054 ,  H01L29/0649 ,  H01L29/66651 ,  H01L29/78654 ,  H01L29/78687

    摘要： The insulated-gate field-effect transistor includes a substrate surmounted by a layer of silicon-germanium alloy, the ratio of the germanium concentration to the silicon concentration of which increases towards the surface of the substrate. The transistor is formed on the active zone in the silicon-germanium alloy layer and lies between two isolating zones. The transistor includes a narrow heterostructure strained-semiconductor channel including a SiGe alloy layer in compression and a silicon layer in tension, extending between the gate and a dielectric block buried in the substrate.

    摘要翻译： 绝缘栅场效应晶体管包括由硅 - 锗合金层覆盖的衬底，其锗浓度与硅浓度之比朝衬底表面增加。 晶体管形成在硅 - 锗合金层的有源区上，位于两个隔离区之间。 晶体管包括窄压电晶体半导体通道，其包括压缩的SiGe合金层和张力的硅层，其在栅极和掩埋在衬底中的介质块之间延伸。

    Electronic component comprising a number of MOSFET transistors and manufacturing method
    10.
    发明授权
    Electronic component comprising a number of MOSFET transistors and manufacturing method 有权
    包括多个MOSFET晶体管的电子元件及其制造方法

    公开(公告)号：US08772879B2

    公开(公告)日：2014-07-08

    申请号：US13488038

    申请日：2012-06-04

    申请人： Jean-Luc Huguenin ,  Stéphane Monfray

    发明人： Jean-Luc Huguenin ,  Stéphane Monfray

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/823842 ,  H01L21/76232 ,  H01L21/82345 ,  H01L29/66484 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/78648

    摘要： An electronic component including a number of insulated-gate field effect transistors, said transistors belonging to at least two distinct subsets by virtue of their threshold voltage, wherein each transistor includes a gate that has two electrodes, namely a first electrode embedded inside the substrate where the channel of the transistor is defined and a second upper electrode located above the substrate facing buried electrode relative to channel and separated from said channel by a layer of dielectric material and wherein the embedded electrodes of all the transistors are formed by an identical material, the upper electrodes having a layer that is in contact with the dielectric material which is formed by materials that differ from one subset of transistors to another.

    摘要翻译： 一种包括多个绝缘栅场效应晶体管的电子部件，所述晶体管由于其阈值电压而属于至少两个不同的子集，其中每个晶体管包括具有两个电极的栅极，即嵌入基板内的第一电极， 限定晶体管的沟道，并且第二上电极位于衬底面对掩埋电极的上方，相对于沟道并且通过介电材料层与所述沟道分离，并且其中所有晶体管的嵌入电极由相同的材料形成， 上部电极具有与电介质材料接触的层，该层由不同于晶体管的一个子集的材料形成。