公开(公告)号：US07906381B2

公开(公告)日：2011-03-15

申请号：US12167282

申请日：2008-07-03

申请人： Nicolas Loubet ,  Didier Dutartre ,  Stéphane Monfray

发明人： Nicolas Loubet ,  Didier Dutartre ,  Stéphane Monfray

IPC分类号： H01L21/84

CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1207

摘要： A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.

摘要翻译： 提供了一种用于在单个衬底中制造第一和第二类型的晶体管的方法。 衬底的第一和第二活性区由横向隔离沟槽区限定，并且去除第二活性区的一部分，使得第二活性区位于第一活性区以下。 第一和第二层半导体材料形成在第二有源区上，使得第二层基本上处于与第一活性区相同的平面。 在第一活性区和第二层产生绝缘栅。 选择性地去除至少一个隔离沟槽区域，并且选择性地去除第一层，以便在第二层下形成隧道。 隧道填充有电介质材料以使第二层与衬底的第二活性区绝缘。 还提供了这种集成电路。

公开(公告)号：US06852993B2

公开(公告)日：2005-02-08

申请号：US10429908

申请日：2003-05-05

申请人： Stéphane Monfray ,  Didier Dutartre ,  Frédéric Boeuf

发明人： Stéphane Monfray ,  Didier Dutartre ,  Frédéric Boeuf

IPC分类号： H01S5/34 ,  H01L29/06 ,  H01L31/072 ,  H01L31/109

CPC分类号： B82Y20/00 ,  H01S5/341 ,  H01S5/3412 ,  Y10S438/962

摘要： An integrated circuit includes a semiconductor device forming a single photon source, and includes a MOS transistor on a silicon substrate. The MOS transistor has a mushroom shaped gate for outputting a single electron on its drain in a controlled manner in response to a control voltage applied to its gate. The transistor also includes at least one silicon compatible quantum box. The quantum box is electrically coupled to the drain region of the transistor, and is capable of outputting a single photon on reception of a single electron emitted by the transistor.

摘要翻译： 集成电路包括形成单个光子源的半导体器件，并且在硅衬底上包括MOS晶体管。 MOS晶体管具有蘑菇形栅极，用于响应于施加到其栅极的控制电压以受控的方式在其漏极上输出单个电子。 晶体管还包括至少一个硅兼容的量子盒。 量子盒电耦合到晶体管的漏极区域，并且能够在接收由晶体管发射的单个电子器件时输出单个光子。

公开(公告)号：US20090023275A1

公开(公告)日：2009-01-22

申请号：US12175877

申请日：2008-07-18

申请人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

发明人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

IPC分类号： H01L21/20

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639

摘要： A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.

摘要翻译： 一种用于制造硅载体中各种晶体取向硅阱的方法，包括以下步骤：在具有第二取向的硅衬底上形成具有第一取向的硅层; 形成绝缘壁，限定阱至少向下延伸到硅衬底和硅层之间的边界; 在外延反应器中，在700℃至950℃的温度范围内，通过盐酸在第一个阱中进行硅层的化学气相蚀刻（CVE）。 并且在第一个阱中，在硅和盐酸的前体存在下，在700℃和900℃之间的温度范围内，在硅衬底上进行气相外延，直到上述表面 硅层。

公开(公告)号：US20070190754A1

公开(公告)日：2007-08-16

申请号：US11704638

申请日：2007-02-09

申请人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

发明人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

IPC分类号： H01L21/20

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639

摘要： A method for forming a single-crystal semiconductor layer portion above a hollowed area, including growing by selective epitaxy on an active single-crystal semiconductor region a sacrificial single-crystal semiconductor layer and a single-crystal semiconductor layer, and removing the sacrificial layer. The epitaxial growth is performed while the active region is surrounded with a raised insulating layer and the removal of the sacrificial single-crystal semiconductor layer is performed through an access resulting from an at least partial removal of the raised insulating layer.

摘要翻译： 一种用于在中空区域上方形成单晶半导体层部分的方法，包括通过牺牲单晶半导体层和单晶半导体层在活性单晶半导体区域上的选择性外延生长，以及去除牺牲层。 在有源区域被凸起的绝缘层围绕的同时进行外延生长，并且通过由至少部分去除凸起的绝缘层获得的访问来执行牺牲单晶半导体层的去除。

公开(公告)号：US07776679B2

公开(公告)日：2010-08-17

申请号：US12175877

申请日：2008-07-18

申请人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

发明人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

IPC分类号： H01L21/8238

CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639

摘要： A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.

摘要翻译： 一种用于制造硅载体中各种晶体取向硅阱的方法，包括以下步骤：在具有第二取向的硅衬底上形成具有第一取向的硅层; 形成绝缘壁，限定阱至少向下延伸到硅衬底和硅层之间的边界; 在外延反应器中，在700℃至950℃的温度范围内，通过盐酸在第一个阱中进行硅层的化学气相蚀刻（CVE）。 并且在第一个阱中，在硅和盐酸的前体存在下，在700℃和900℃之间的温度下，在硅衬底上进行气相外延，直到 硅层。

公开(公告)号：US20070074652A1

公开(公告)日：2007-04-05

申请号：US11523824

申请日：2006-09-14

申请人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

发明人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C30B25/18 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02661

摘要： A method for low-temperature epitaxy at the surface of at least one plate made of a pure silicon- or silicon alloy (SiGe, SiC, SiGeC . . . )-based material, in a chemical vapor deposition (CVD) system, in particular a rapid thermal (RTCVD) system, which method includes the following steps: loading the plate into the equipment, at a loading temperature, preparing the surface for the deposition of new chemical species, and after preparing the surface, performing the deposition under low-temperature epitaxy conditions (>750° C.), in which method the preparation of the surface includes a step of passivation of the surface by injection of an active gas, or gas mixture.

摘要翻译： 特别是在化学气相沉积（CVD）系统中由纯硅或硅合金（SiGe，SiC，SiGeC ...）基材料制成的至少一块板表面的低温外延方法 一种快速热（RTCVD）系统，该方法包括以下步骤：在装载温度下将板装载到设备中，制备用于沉积新化学物质的表面，并且在制备表面之后，在低温下进行沉积， 温度外延条件（> 750℃），其中制备表面的方法包括通过注入活性气体或气体混合物钝化表面的步骤。

公开(公告)号：US20120252174A1

公开(公告)日：2012-10-04

申请号：US13434923

申请日：2012-03-30

申请人： Didier Dutartre ,  Nicolas Loubet ,  Yves Campidelli ,  Denis Pellissier-Tanon

发明人： Didier Dutartre ,  Nicolas Loubet ,  Yves Campidelli ,  Denis Pellissier-Tanon

IPC分类号： H01L21/336 ,  H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7848

摘要： A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor.

摘要翻译： 在单晶半导体结构和多晶半导体结构上外延生长半导体材料层。 然后蚀刻外延层，以便在单晶结构上保留所述材料的非零厚度，并在多晶结构上保持零厚度。 在每个重复中，使用相同的材​​料或不同的材料重复生长和蚀刻的过程，直到所述单晶结构上的一叠外延层已经达到期望的厚度。 单晶结构优选为晶体管的源/漏区，多晶结构优选为该晶体管的栅极。

公开(公告)号：US07776745B2

公开(公告)日：2010-08-17

申请号：US11704799

申请日：2007-02-09

申请人： Nicolas Loubet ,  Didier Dutartre ,  Alexandre Talbot ,  Laurent Rubaldo

发明人： Nicolas Loubet ,  Didier Dutartre ,  Alexandre Talbot ,  Laurent Rubaldo

IPC分类号： H01L21/302

CPC分类号： H01L21/306 ,  H01L21/3065

摘要： A method for selectively etching single-crystal silicon-germanium in the presence of single-crystal silicon, including a chemical etch based on hydrochloric acid in gaseous phase at a temperature lower than approximately 700° C.

摘要翻译： 在单晶硅存在下选择性蚀刻单晶硅锗的方法，包括在低于大约700℃的温度下在气相中基于盐酸的化学蚀刻。

公开(公告)号：US07622368B2

公开(公告)日：2009-11-24

申请号：US11704638

申请日：2007-02-09

申请人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

发明人： Didier Dutartre ,  Nicolas Loubet ,  Alexandre Talbot

IPC分类号： H01L21/20 ,  H01L21/36

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639

摘要： A method for forming a single-crystal semiconductor layer portion above a hollowed area, including growing by selective epitaxy on an active single-crystal semiconductor region a sacrificial single-crystal semiconductor layer and a single-crystal semiconductor layer, and removing the sacrificial layer. The epitaxial growth is performed while the active region is surrounded with a raised insulating layer and the removal of the sacrificial single-crystal semiconductor layer is performed through an access resulting from an at least partial removal of the raised insulating layer.

摘要翻译： 一种用于在中空区域上方形成单晶半导体层部分的方法，包括通过牺牲单晶半导体层和单晶半导体层在活性单晶半导体区域上的选择性外延生长，以及去除牺牲层。 在有源区域被凸起的绝缘层围绕的同时进行外延生长，并且通过由至少部分去除凸起的绝缘层获得的访问来执行牺牲单晶半导体层的去除。

公开(公告)号：US08168536B2

公开(公告)日：2012-05-01

申请号：US12101744

申请日：2008-04-11

申请人： Didier Dutartre ,  Philippe Coronel ,  Nicolas Loubet

发明人： Didier Dutartre ,  Philippe Coronel ,  Nicolas Loubet

IPC分类号： H01L21/44

CPC分类号： H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545

摘要： Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region of the substrate surface (for example, through epitaxial growth). The growth material is surrounded by an insulating material. The grown material is then removed to form a void in the insulating material which coincides with the desired location of the metal contact. This removal of the grown material exposes the region on the substrate surface. Conductive material is then deposited to fill the void and thus form the metal contact directly with the region of the substrate surface.

摘要翻译： 金属触点自动定位在半导体产品的晶片上。 通过在衬底表面的区域上的生长材料的选择性沉积（例如，通过外延生长）来确定金属接触的相应放置区域。 生长材料被绝缘材料包围。 然后移除生长的材料以在绝缘材料中形成与金属接触件的期望位置重合的空隙。 这种去除生长的材料暴露在衬底表面上的区域。 然后沉积导电材料以填充空隙，从而直接与基底表面的区域形成金属接触。