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    PRIVACY PROTECTED INPUT-OUTPUT PORT CONTROL
    1.
    发明申请
    PRIVACY PROTECTED INPUT-OUTPUT PORT CONTROL 有权

    公开(公告)号：US20170177846A1

    公开(公告)日：2017-06-22

    申请号：US14978578

    申请日：2015-12-22

    申请人： Nitin V. Sarangdhar ,  Raul Gutierrez

    发明人： Nitin V. Sarangdhar ,  Raul Gutierrez

    IPC分类号： G06F21/32 ,  G06F21/62

    CPC分类号： G06F21/32 ,  G06F21/62

    摘要： Systems and techniques for privacy protected input-output port control are described herein. In an example, an indication may be obtained that a protected port is disabled. A set of application attributes stored in a secure memory location may be compared to a set of attested application attributes to create a verification flag. At least one port attribute of the protected port may be obtained based on the verification flag. The protected port may be enabled using the at least one port attribute. Other examples, for controlling an input-output port using computer firmware and trusted execution techniques are further disclosed.

    Boundary detection in media streams
    5.
    发明授权
    Boundary detection in media streams 有权
    媒体流中的边界检测

    公开(公告)号：US08521006B2

    公开(公告)日：2013-08-27

    申请号：US12775003

    申请日：2010-05-06

    申请人： Daniel Nemiroff ,  Balaji Vembu ,  Raul Gutierrez ,  Suryaprasad Kareenahalli

    发明人： Daniel Nemiroff ,  Balaji Vembu ,  Raul Gutierrez ,  Suryaprasad Kareenahalli

    IPC分类号： H04N5/94

    CPC分类号： G11B27/3027 ,  G11B27/28

    摘要： Encoded data decoding techniques. A data decoding agent determines a data segment size for a packet that includes a header and a data segment. The data decoding agent determines a segment end location based, at least in part, on the data segment size. The data decoding agent processes subblocks of data from the data segment. The data decoding agent compares a current location to the segment end location to determine if a current subblock of data from the data segments contains the segment end location. The data decoding agent triggers an exception handler if the current subblock contains the segment end location.

    摘要翻译： 编码数据解码技术。 数据解码代理确定包括报头和数据段的分组的数据段大小。 数据解码代理至少部分地基于数据段大小来确定段结束位置。 数据解码代理处理来自数据段的数据的子块。 数据解码代理将当前位置与段结束位置进行比较，以确定来自数据段的当前数据子块是否包含段结束位置。 如果当前子块包含段结束位置，则数据解码代理触发异常处理程序。

    DIRECT MEMORY ACCESS ENGINE PHYSICAL MEMORY DESCRIPTORS FOR MULTI-MEDIA DEMULTIPLEXING OPERATIONS
    6.
    发明申请
    DIRECT MEMORY ACCESS ENGINE PHYSICAL MEMORY DESCRIPTORS FOR MULTI-MEDIA DEMULTIPLEXING OPERATIONS 有权
    直接存储器访问引擎用于多媒体解复用操作的物理存储器描述符

    公开(公告)号：US20110320777A1

    公开(公告)日：2011-12-29

    申请号：US12824300

    申请日：2010-06-28

    申请人： DANIEL NEMIROFF ,  Balaji Vembu ,  Raul Gutierrez ,  Suryaprasad Kareenahalli

    发明人： DANIEL NEMIROFF ,  Balaji Vembu ,  Raul Gutierrez ,  Suryaprasad Kareenahalli

    IPC分类号： G06F9/38

    CPC分类号： G06F9/5027

    摘要： The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.

    摘要翻译： 本文描述的架构和技术可以改善系统性能。 两个相互依赖的硬件引擎之间的通信是管道的一部分，使得引擎在引擎完成工作时同步以消耗资源。 当管道的上一个阶段完成时，减少软件/固件从硬件管道的每个阶段的角色。 减少用于软件初始化的硬件描述符的内存分配，以通过减少由于软件交互而导致的流水线停顿来提高性能。

    High performance chipset prefetcher for interleaved channels
    7.
    发明申请
    High performance chipset prefetcher for interleaved channels 有权
    用于交错通道的高性能芯片组预取器

    公开(公告)号：US20070005934A1

    公开(公告)日：2007-01-04

    申请号：US11172401

    申请日：2005-06-29

    申请人： Hemant Rotithor ,  Abhishek Singhal ,  Randy Osborne ,  Zohar Bogin ,  Raul Gutierrez ,  Buderya Acharya ,  Surya Kareenahalli

    发明人： Hemant Rotithor ,  Abhishek Singhal ,  Randy Osborne ,  Zohar Bogin ,  Raul Gutierrez ,  Buderya Acharya ,  Surya Kareenahalli

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862 ,  G06F12/0215 ,  G06F12/0607 ,  G06F2212/6022 ,  G06F2212/6026

    摘要： The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.

    摘要翻译： 本发明包括一种从具有交织信道的存储装置预取的装置和方法。 芯片组预取器包括用于检测流中的步幅的步幅检测器，用于将预取插入存储器件的预取注入器，用于将预取映射到存储器件的每个通道的通道映射器，调度器以将预取计划到存储器上 DRAM状态感知方式的设备，限制预取数量的限制启发式，以及预取数据缓冲器来存储预取数据。 预取方法包括跟踪流的状态，检测一条流上的步幅，选择用于预取注入的步幅的流，从所选择的流中引入预取，将预取映射到每个交错通道，注入预取 从所选择的流到每个交织的信道，并且以DRAM状态感知的方式将预取调度到存储器设备上。

    Direct memory access engine physical memory descriptors for multi-media demultiplexing operations
    9.
    发明授权
    Direct memory access engine physical memory descriptors for multi-media demultiplexing operations 有权
    用于多媒体解复用操作的直接内存访问引擎物理内存描述符

    公开(公告)号：US08509254B2

    公开(公告)日：2013-08-13

    申请号：US12824300

    申请日：2010-06-28

    申请人： Daniel Nemiroff ,  Balaji Vembu ,  Raul Gutierrez ,  Suryaprasad Kareenahalli

    发明人： Daniel Nemiroff ,  Balaji Vembu ,  Raul Gutierrez ,  Suryaprasad Kareenahalli

    IPC分类号： G06F12/00

    CPC分类号： G06F9/5027

    摘要： The architecture and techniques described herein can improve system performance with respect to the following. Communication between two interdependent hardware engines, that are part of pipeline, such that the engines are synchronized to consume resources when the engines are done with the work. Reduction of the role of software/firmware from feeding each stage of the hardware pipeline when the previous stage of the pipeline has completed. Reduction in the memory allocation for software-initialized hardware descriptors to improve performance by reducing pipeline stalls due to software interaction.

    摘要翻译： 本文描述的架构和技术可以改善系统性能。 两个相互依赖的硬件引擎之间的通信是管道的一部分，使得引擎在引擎完成工作时同步以消耗资源。 当管道的上一个阶段完成时，减少软件/固件从硬件管道的每个阶段的角色。 减少用于软件初始化的硬件描述符的内存分配，以通过减少由于软件交互而导致的流水线停顿来提高性能。