System and method for controlling at least two power semiconductors connected in parallel
    3.
    发明授权
    System and method for controlling at least two power semiconductors connected in parallel 有权
    用于控制并联连接的至少两个功率半导体的系统和方法

    公开(公告)号:US09000827B2

    公开(公告)日:2015-04-07

    申请号:US13512041

    申请日:2010-12-01

    IPC分类号: H03K17/06 H03K17/12

    摘要: A system includes at least two power semiconductor chips being connected in parallel and including each a gate terminal for switching the power semiconductor chip in a blocking-state by a first gate voltage and for switching the power semiconductor chip in a conducting-state by a second gate voltage. The system includes further a control device adapted for applying the first or the second gate voltage to the gate terminals of the at least two power semiconductor chips. The control device is adapted for applying a third gate voltage to the gate terminal of the at least one remaining power semiconductor chip when a power semiconductor chip fails, and that the third gate voltage is higher than the second gate voltage.

    摘要翻译: 一种系统包括并联连接的至少两个功率半导体芯片,每个功率半导体芯片包括:每个栅极端子,用于通过第一栅极电压将功率半导体芯片以阻塞状态切换,并将功率半导体芯片以导通状态切换第二栅极电压 栅极电压。 该系统还包括适于将第一或第二栅极电压施加到至少两个功率半导体芯片的栅极端子的控制装置。 所述控制装置适于在功率半导体芯片发生故障时向所述至少一个剩余功率半导体芯片的栅极端子施加第三栅极电压,并且所述第三栅极电压高于所述第二栅极电压。

    SYSTEM AND METHOD FOR CONTROLLING AT LEAST TWO POWER SEMICONDUCTORS CONNECTED IN PARALLEL
    4.
    发明申请
    SYSTEM AND METHOD FOR CONTROLLING AT LEAST TWO POWER SEMICONDUCTORS CONNECTED IN PARALLEL 有权
    用于控制并联连接的最小二功率半导体的系统和方法

    公开(公告)号:US20120262218A1

    公开(公告)日:2012-10-18

    申请号:US13512041

    申请日:2010-12-01

    IPC分类号: H03K17/06

    摘要: A system includes at least two power semiconductor chips being connected in parallel and including each a gate terminal for switching the power semiconductor chip in a blocking-state by a first gate voltage and for switching the power semiconductor chip in a conducting-state by a second gate voltage. The system includes further a control device adapted for applying the first or the second gate voltage to the gate terminals of the at least two power semiconductor chips. The control device is adapted for applying a third gate voltage to the gate terminal of the at least one remaining power semiconductor chip when a power semiconductor chip fails, and that the third gate voltage is higher than the second gate voltage.

    摘要翻译: 一种系统包括并联连接的至少两个功率半导体芯片,每个功率半导体芯片包括:每个栅极端子,用于通过第一栅极电压将功率半导体芯片以阻塞状态切换,并将功率半导体芯片以导通状态切换第二栅极电压 栅极电压。 该系统还包括适于将第一或第二栅极电压施加到至少两个功率半导体芯片的栅极端子的控制装置。 所述控制装置适于在功率半导体芯片发生故障时向所述至少一个剩余功率半导体芯片的栅极端子施加第三栅极电压,并且所述第三栅极电压高于所述第二栅极电压。