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公开(公告)号：US09566613B2
公开(公告)日：2017-02-14
申请号：US13861579
申请日：2013-04-12
摘要： An oscillation sieve, including a screen; an oscillator oscillating the screen to sieve a material; a feeder feeding the material onto the screen; a collector collecting the material having passed the screen; a remover removing the material not having passed the screen therefrom; a guide member fixed on the screen, guiding the material fed from the feeder and not having passed the screen to the remover, wherein the guide member is spiral member formed of an elastic material capable of following the oscillating screen.
摘要翻译： 振动筛，包括筛网; 振荡器振荡筛网以筛选材料; 将材料供给到筛网上的进料器; 收集已经通过筛网的材料的收集器; 除去未经过筛网的材料的去除剂; 引导构件，其固定在所述屏幕上，将从所述供给器供给的材料引导并且没有通过所述屏幕到所述移除器，其中，所述引导构件是由能够跟随所述振动筛的弹性材料形成的螺旋构件。
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公开(公告)号：US20130327685A1
公开(公告)日：2013-12-12
申请号：US13861579
申请日：2013-04-12
IPC分类号： B07B1/38
摘要： An oscillation sieve, including a screen; an oscillator oscillating the screen to sieve a material; a feeder feeding the material onto the screen; a collector collecting the material having passed the screen; a remover removing the material not having passed the screen therefrom; a guide member fixed on the screen, guiding the material fed from the feeder and not having passed the screen to the remover, wherein the guide member is spiral member formed of an elastic material capable of following the oscillating screen.
摘要翻译： 振动筛，包括筛网; 振荡器振荡屏幕以筛选材料; 将材料供给到筛网上的进料器; 收集已经通过筛网的材料的收集器; 除去未经过筛网的材料的去除剂; 引导构件，其固定在所述屏幕上，将从所述供给器供给的材料引导并且没有通过所述屏幕到所述移除器，其中，所述引导构件是由能够跟随所述振动筛的弹性材料形成的螺旋构件。
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3.发明授权Semiconductor storage device, semiconductor device, and manufacturing method therefor 有权半导体存储装置，半导体装置及其制造方法公开(公告)号：US08039940B2
公开(公告)日：2011-10-18
申请号：US11956358
申请日：2007-12-14
申请人： Kohji Kanamori , Teiichirou Nishizaka , Noriaki Kodama , Isao Katayama , Yoshihiro Matsuura , Kaoru Ishihara , Yasushi Harada , Naruaki Minenaga , Chihiro Oshita
发明人： Kohji Kanamori , Teiichirou Nishizaka , Noriaki Kodama , Isao Katayama , Yoshihiro Matsuura , Kaoru Ishihara , Yasushi Harada , Naruaki Minenaga , Chihiro Oshita
IPC分类号： H01L23/26
CPC分类号： H01L23/26 , H01L21/3221 , H01L23/3128 , H01L24/48 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/12032 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.
摘要翻译： 根据本发明，在半导体芯片的侧表面和底表面上沉积吸气层。 然后将半导体芯片安装在封装的板上，使得在底表面上形成肖特基势垒。 通过这种结构，可以通过沉积在半导体芯片的侧表面和/或底表面上的缺陷层和肖特基势垒捕获穿过封装板的金属离子。
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4.发明申请SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF CONTROLLING A SEMICONDUCTOR MEMORY DEVICE 有权半导体存储器件和控制半导体存储器件的方法公开(公告)号：US20110075500A1
公开(公告)日：2011-03-31
申请号：US12892462
申请日：2010-09-28
申请人： Noriaki Kodama , Takuji Onuma
发明人： Noriaki Kodama , Takuji Onuma
IPC分类号： G11C17/16
摘要： A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated by N-wells of an opposite conductivity type, formed therebetween.
摘要翻译： 半导体存储器件包括分别由晶体管构成的第一抗熔丝元件和第二抗熔丝元件，其中第一抗熔丝元件和第二抗熔丝元件被配置为可以并行编程，分别形成 在衬底上的P阱中，并且相邻P阱由在其间形成的相反导电类型的N阱分离。
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公开(公告)号：US20070227664A1
公开(公告)日：2007-10-04
申请号：US11694083
申请日：2007-03-30
申请人： Naoki MATSUMOTO , Yoshinobu Hayakawa , Hidetoshi Hanaoka , Noriaki Kodama , Chishio Koshimizu , Manabu Iwata , Satoshi Tanaka
发明人： Naoki MATSUMOTO , Yoshinobu Hayakawa , Hidetoshi Hanaoka , Noriaki Kodama , Chishio Koshimizu , Manabu Iwata , Satoshi Tanaka
CPC分类号： H01J37/32174 , H01J37/32091
摘要： A plasma processing apparatus includes a processing vessel capable of being vacuum evacuated; a first electrode disposed in the processing vessel in a state electrically floating via an insulating member or a space; a second electrode, arranged in the processing vessel to face and be in parallel to the first electrode with a specific interval, supporting a substrate to be processed; a processing gas supply unit for supplying a desired processing gas into a processing space surrounded by the first electrode, the second electrode and a sidewall of the processing vessel; and a first radio frequency power supply unit for applying a first radio frequency power to the second electrode to generate a plasma of the processing gas in the processing space. An electrostatic capacitance between the first electrode and the processing vessel is set such that a desired plasma density distribution is obtained for the generated plasma.
摘要翻译： 一种等离子体处理装置，其特征在于，包括：真空抽真空处理容器; 以处于通过绝缘构件或空间电浮动的状态设置在处理容器中的第一电极; 第二电极，布置在处理容器中以特定间隔面对并平行于第一电极，支撑待处理的基板; 处理气体供给单元，用于将期望的处理气体供给到被处理容器的第一电极，第二电极和侧壁包围的处理空间中; 以及第一射频电源单元，用于向所述第二电极施加第一射频功率以在所述处理空间中产生所述处理气体的等离子体。 第一电极和处理容器之间的静电电容被设定为使得所产生的等离子体获得期望的等离子体密度分布。
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6.发明申请公开(公告)号：US20050280074A1
公开(公告)日：2005-12-22
申请号：US11154517
申请日：2005-06-17
申请人： Noriaki Kodama
发明人： Noriaki Kodama
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11556 , H01L27/115 , H01L29/42336 , H01L29/7885
摘要： A nonvolatile semiconductor memory device includes a substrate, a central structure, a second gate insulating film, a floating gate, and a control gate. The substrate has a trench. The central structure is formed so as to be embedded in the trench and protruded from the substrate. The second gate insulating film is formed on the substrate so as to be contact with the central structure. The floating gate is formed on the second gate insulating film. The control gate is formed so as to cover the floating gate through a insulating film;. The central structure includes an assistant gate and a first gate insulating film which is formed such that the assistance gate is surrounded with the first gate insulating film. The floating gate is formed in a side wall shape on the side surface of the central structure.
摘要翻译： 非易失性半导体存储器件包括衬底，中心结构，第二栅极绝缘膜，浮动栅极和控制栅极。 衬底具有沟槽。 中心结构被形成为嵌入沟槽并从衬底突出。 第二栅极绝缘膜形成在基板上以便与中心结构接触。 浮置栅极形成在第二栅极绝缘膜上。 控制栅极形成为通过绝缘膜覆盖浮动栅极; 中心结构包括辅助栅极和第一栅极绝缘膜，其形成为辅助栅极被第一栅极绝缘膜包围。 浮栅在中心结构的侧面形成为侧壁形状。
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公开(公告)号：US5808940A
公开(公告)日：1998-09-15
申请号：US828757
申请日：1997-03-25
申请人： Noriyuki Ohta , Noriaki Kodama , Toshikatsu Jinbo
发明人： Noriyuki Ohta , Noriaki Kodama , Toshikatsu Jinbo
CPC分类号： G11C16/30
摘要： A nonvolatile semiconductor memory includes a cell array prepared by arranging erasable and programmable memory cell transistors in rows and columns, word lines arranged in correspondence with the respective rows of the cell array and connected to the control gates of the memory cell transistors, digit lines arranged in correspondence with the respective columns of the cell array and connected to the drains of the memory cell transistors, source lines connected to the sources of the memory cell transistors, and a source power supply circuit for applying a source voltage to the source lines in an erase operation. This memory erases by the source voltage data in the memory cell transistors in the rows and columns of the cell array. The source power supply circuit is a circuit including a first P-channel transistor which sets a current to be supplied to the source lines to a predetermined value in the erase operation in a range wherein the source voltage is lower than a predetermined potential, and a second P-channel transistor which sets the current to be supplied to the source lines so as to decrease faster than the current decreased by the characteristic of the first transistor with an increase in source voltage in a range wherein the source voltage is higher than the predetermined potential.
摘要翻译： 非易失性半导体存储器包括通过以行和列排列可擦除可编程存储单元晶体管而制备的单元阵列，与单元阵列的各行相对应地布置并连接到存储单元晶体管的控制栅极的字线，布置的数字线 与电池阵列的各列对应并连接到存储单元晶体管的漏极，连接到存储单元晶体管的源极的源极线和用于将源极电压施加到源极线的源极电源电路 擦除操作。 该存储器由单元阵列的行和列中的存储单元晶体管中的源电压数据擦除。 源极电源电路是包括第一P沟道晶体管的电路，该第一P沟道晶体管在源极电压低于预定电位的范围内将要提供给源极线的电流设置在擦除操作中的预定值，并且 第二P沟道晶体管，其设置要提供给源极线的电流，以便在源极电压高于预定的范围内，随着源极电压的增加，电流降低得比第一晶体管的特性减小的电流快。 潜在。
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8.发明授权Method for erasing data stored in a non-volatile semiconductor memory by using a predetermined series of pulses 失效通过使用预定的一系列脉冲来擦除存储在非易失性半导体存储器中的数据的方法
公开(公告)号：US5361235A
公开(公告)日：1994-11-01
申请号：US865442
申请日：1992-04-09
申请人： Noriaki Kodama
发明人： Noriaki Kodama
CPC分类号： G11C16/14
摘要： A method for erasing data stored in a non-volatile semiconductor memory is applied to a memory cell transistor including a p-type well region, a source and a drain formed within the p-type well region, and a composite gate including a floating gate electrode formed on the p-type well region. In the method, a plurality of pulses having a high positive voltage is applied to the p-type well region so that a product (I.times.N) of a pulse interval (I) and a number of the plurality of pulses (N) becomes not smaller than 0.1 s on condition that the control gate electrode is fixed to the ground level and the source and drain are kept at a floating state.
摘要翻译： 一种用于擦除存储在非易失性半导体存储器中的数据的方法被应用于包括在p型阱区中形成的p型阱区，源极和漏极的存储单元晶体管，以及包括浮置栅极的复合栅极 电极形成在p型阱区上。 在该方法中，向p型阱区域施加具有高正电压的多个脉冲，使得脉冲间隔（I）和多个脉冲数（N）的乘积（IxN）不小于 条件是控制栅电极固定在地电平上，而源极和漏极保持在浮置状态。
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9.发明授权Semiconductor memory device and a method of controlling a semiconductor memory device 有权半导体存储器件和控制半导体存储器件的方法公开(公告)号：US08259528B2
公开(公告)日：2012-09-04
申请号：US12892462
申请日：2010-09-28
申请人： Noriaki Kodama , Takuji Onuma
发明人： Noriaki Kodama , Takuji Onuma
IPC分类号： G11C17/18
摘要： A semiconductor memory device includes a first anti-fuse element and a second anti-fuse element, respectively composed of a transistor, wherein the first anti-fuse element and the second anti-fuse element are configured so as to be concomitantly programmable, respectively formed in P-wells on a substrate, and the adjacent P-wells are isolated by N-wells of an opposite conductivity type, formed therebetween.
摘要翻译： 半导体存储器件包括分别由晶体管构成的第一抗熔丝元件和第二抗熔丝元件，其中第一抗熔丝元件和第二抗熔丝元件被配置为可以并行编程，分别形成 在衬底上的P阱中，并且相邻P阱由在其间形成的相反导电类型的N阱分离。
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公开(公告)号：US20110122672A1
公开(公告)日：2011-05-26
申请号：US12931159
申请日：2011-01-26
IPC分类号： G11C17/16 , H01L27/105
CPC分类号： H01L27/112 , G11C17/16 , H01L27/11206
摘要： A non-volatile semiconductor memory device having a memory cell in which operating potentials are few and the scale of the peripheral circuitry is reduced includes a select transistor having a source/drain on both sides of a channel of a semiconductor substrate and having a gate electrode disposed on the channel via a thick gate insulating film; an element isolation region formed on the semiconductor substrate in an area adjacent to the select transistor; an antifuse adjacent to the element isolation region, having a lower electrode formed on the semiconductor substrate and having an upper electrode disposed on the semiconductor substrate in an area between the element isolation region and lower electrode via a thin gate insulating film; and a connection contact electrically connecting the source and upper electrode and contacting the source and the upper electrode.
摘要翻译： 一种非易失性半导体存储器件，具有其中工作电位很小并且外围电路的规模减小的存储单元包括在半导体衬底的通道两侧具有源极/漏极的选择晶体管，并具有栅电极 通过厚栅绝缘膜设置在通道上; 在与所述选择晶体管相邻的区域中形成在所述半导体衬底上的元件隔离区; 邻近元件隔离区域的反熔丝，其具有形成在半导体衬底上的下电极，并且具有通过薄栅绝缘膜在元件隔离区和下电极之间的区域中设置在半导体衬底上的上电极; 以及电连接源极和上部电极并接触源极和上部电极的连接接点。
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