公开(公告)号：US4769781A

公开(公告)日：1988-09-06

申请号：US925374

申请日：1986-10-30

申请人： Norihisa Shirota ,  Shinji Takada ,  Kazuo Yamagiwa

发明人： Norihisa Shirota ,  Shinji Takada ,  Kazuo Yamagiwa

IPC分类号： G06F13/12 ,  G06F3/00 ,  G06F13/14 ,  G06F13/20 ,  G06F13/38 ,  G06F13/42 ,  G11C19/00 ,  H04Q9/00 ,  G06F13/00

CPC分类号： G06F13/4291

摘要： An IC device has a first terminal for inputting date in the format for a four-line or two-line type bus line, and for outputting data, a second terminal for receiving a chip select signal, a third terminal for receiving a clock pulse, a fourth terminal for outputting data a first signal processor for receiving data from the first terminal in the format for a two-line type bus line and including an address signal and for outputting the data such first signal processor including a detector for detecting the address signal, a second signal processor for receiving the data supplied from the first terminal in the format of a four-line type bus line and outputting the data to the fourth terminal, the first and second signal processors being selectively enabled in accordance with the chip select signal, and a control unit for receiving the signal from the first or second signal processor and outputting the data to the first terminal or the first or second signal processors.

摘要翻译： IC器件具有用于以四线或双线型总线的格式输入日期的第一端子，并且用于输出数据，用于接收芯片选择信号的第二端子，用于接收时钟脉冲的第三端子， 用于输出数据的第四终端，用于以二线式总线的格式接收来自第一终端的数据并包括地址信号的第一信号处理器，并且用于输出数据，第一信号处理器包括用于检测地址信号的检测器 第二信号处理器，用于以四线式总线的格式接收从第一终端提供的数据，并将数据输出到第四终端，第一和第二信号处理器根据片选信号选择性地使能 以及控制单元，用于从第一或第二信号处理器接收信号，并将数据输出到第一终端或第一或第二信号处理器。

公开(公告)号：US5341385A

公开(公告)日：1994-08-23

申请号：US950779

申请日：1992-09-24

申请人： Norihisa Shirota

发明人： Norihisa Shirota

IPC分类号： H03M13/03 ,  H03M13/15 ,  H03M13/00

CPC分类号： H03M13/151 ,  H03M13/033

摘要： A decoding method of Reed-Solomon code produces an error position polynomial .sigma.(x) and an error evaluation polynomial .omega.(x) by a Euclidean algorithm, whereby a syndrome polynomial S(x) is obtained, the highest degrees of the syndrome polynomial S(x) and of an initial polynomial x.sup.2t, which is determined by the number t of symbols to be corrected, are multiplied, while the degree is incrementally reduced, thereby obtaining polynomials h(x) and g(x) that satisfy the relation:f(x).multidot.B(x)+g(x).multidot.S(x)=h(x)(where the degree of h(x) is less than the degree of g(x).ltoreq.t). The polynomial g(x) is set to the error position polynomial .sigma.(x), and the polynomial h(x) is set to the error evaluation polynomial .omega.(x), thereby performing the decoding by real time processing.

摘要翻译： Reed-Solomon码的解码方法通过欧几里德算法产生误差位置多项式σ（x）和误差评估多项式ω（x），从而得到校正子多项式S（x），校正子多项式S （x）和由要校正的符号数t确定的初始多项式x2t相乘，同时递减地减小程度，从而获得满足以下关系的多项式h（x）和g（x）： f（x）xB（x）+ g（x）xS（x）= h（x）（其中h（x）的程度小于g（x）的程度

公开(公告)号：US5416615A

公开(公告)日：1995-05-16

申请号：US951083

申请日：1992-09-25

申请人： Norihisa Shirota

发明人： Norihisa Shirota

IPC分类号： H03M7/30 ,  G06T9/00 ,  H04N1/41 ,  H04N19/102 ,  H04N19/126 ,  H04N19/134 ,  H04N19/136 ,  H04N19/14 ,  H04N19/149 ,  H04N19/172 ,  H04N19/196 ,  H04N19/423 ,  H04N19/46 ,  H04N19/463 ,  H04N19/50 ,  H04N19/59 ,  H04N19/60 ,  H04N19/61 ,  H04N19/62 ,  H04N19/625 ,  H04N19/65 ,  H04N19/70 ,  H04N19/91 ,  H04N7/30

CPC分类号： H04N19/132 ,  H04N19/126 ,  H04N19/176 ,  H04N19/46 ,  H04N19/60 ,  H04N19/124 ,  H04N19/13 ,  H04N19/146 ,  H04N19/149 ,  H04N19/15 ,  H04N19/91

摘要： A digital data transmitting apparatus comprises: an original block forming circuit for extracting image data in horizontal direction and/or vertical direction at intervals of a predetermined number of samples and forming an original block consisting of (n.times.n) pixel data; a differential block forming circuit for forming a differential block consisting of (m.times.m) pixel data with differential data between adjacent pixel data in horizontal and/or vertical direction and the pixel data concerned; a coding circuit for transform coding the original block and the differential block, respectively; a flag generation circuit for transmitting meaningful data of coefficient data generated by transform coding the differential block and generating a flag representing omission of the transmission of coefficient data where there is no meaningful data; and a transmission circuit for transmitting the flag and the pixel data of each of the block.

摘要翻译： 数字数据发送装置包括：原始块形成电路，用于以预定数量的采样的间隔在水平方向和/或垂直方向上提取图像数据，并形成由（n×n）像素数据组成的原始块; 差分块形成电路，用于形成由水平和/或垂直方向上的相邻像素数据之间的差分数据的像素数据（m×m）组成的差分块和与之相关的像素数据; 分别对原始块和差分块进行变换编码的编码电路; 标志产生电路，用于发送通过对差分块进行变换编码产生的系数数据的有意义的数据，并产生表示省略不存在有意义的数据的系数数据的传输的标志; 以及发送电路，用于发送每个块的标志和像素数据。

公开(公告)号：US4376290A

公开(公告)日：1983-03-08

申请号：US197567

申请日：1980-10-16

申请人： Norihisa Shirota

发明人： Norihisa Shirota

IPC分类号： H04N9/804 ,  H04N5/92 ,  H04N9/808 ,  H04N9/873 ,  H04N9/877 ,  H04N9/888 ,  H04N5/76

CPC分类号： H04N9/888 ,  H04N9/873 ,  H04N9/877

摘要： In apparatus for processing color video information composed of a color video signal having luminance and chrominance components and a respective identifying signal which identifies a phase of the chrominance component, for example, by indicating the frame, field and/or line of which the respective color video signal is a part; the color video signal and respective identifying signal are temporarily stored in a memory and, when the color video signal and the respective identifying signal are simultaneously read out of the memory, a comparison is made between the read-out identifying signal and a corresponding reference or read request signal, and at least the phase of the chrominance component of the read-out color video signal is controlled on the basis of such comparison. In the case where a line of the read-out color video signal is indicated by its respective identifying signal to be of a field which is different from the read request field defined by the then occurring reference or read request signal so that it would be spatially displaced from the corresponding line of the read request field, the value of at least the luminance component in the read-out line is replaced by an interpolated value derived from values of the luminance component in the lines adjacent the read-out line. When a PAL color video signal is being processed, absolute values of color difference signals are derived, for certain sampling points where such color difference signals do not appear, by interpolation of the values for such color difference signals from adjacent sampling points.

摘要翻译： 在用于处理由具有亮度和色度分量的彩色视频信号组成的彩色视频信息的处理装置中，以及用于标识色度分量的相位的各个识别信号，例如通过指示相应颜色的帧，场和/或行 视频信号是一部分; 彩色视频信号和相应的识别信号被临时存储在存储器中，并且当彩色视频信号和相应的识别信号被同时从存储器中读出时，比较读出的识别信号和相应的参考信号 读取请求信号，并且基于这样的比较来控制读出的彩色视频信号的色度分量的至少相位。 在读出的彩色视频信号的一行由其相应的识别信号指示为与由当时出现的参考或读取请求信号定义的读取请求字段不同的字段的情况下，使得它将在空间上 从读取请求字段的相应行移位，至少读出行中的亮度分量的值由从与读出行相邻的行中的亮度分量的值导出的内插值代替。 当正在处理PAL彩色视频信号时，通过对来自相邻采样点的这种色差信号的值进行插值，对于不出现这种色差信号的某些采样点，导出色差信号的绝对值。

公开(公告)号：US5524264A

公开(公告)日：1996-06-04

申请号：US209105

申请日：1994-03-09

申请人： Norihisa Shirota ,  Yasunobu Kato ,  Noboru Oya

发明人： Norihisa Shirota ,  Yasunobu Kato ,  Noboru Oya

IPC分类号： G06F15/80 ,  G06F15/76

CPC分类号： G06F15/8015

摘要： A parallel arithmetic-logical processing device in which arithmetic-logical processing is shared among and executed in a parallel fashion by a plurality of processing elements. The device includes a large-capacity serial access memory for continuous reading/writing of large-scale data, a small-capacity serial access memory for continuous reading/writing of small-scale data and a high-speed general-purpose random access memory for random writing/readout of small-scale data. A central processing unit (CPU) causes the memories to be used or not used depending on the scale of the arithmetic-logical processing. Since the serial access memory executes continuous data writing and reading, high-speed access may be achieved, so that it can be manufactured inexpensively with a large storage capacity. Consequently, the processing speed in the CPU may be increased, while the parallel arithmetic-logical processing device may be manufactured inexpensively.

摘要翻译： 一种并行算术逻辑处理装置，其中算术逻辑处理由多个处理元件以并行方式共享并执行。 该设备包括用于连续读/写大规模数据的大容量串行存取存储器，用于连续读/写小规模数据的小容量串行存取存储器以及高速通用随机存取存储器 随机写入/读出小规模数据。 中央处理单元（CPU）根据算术逻辑处理的规模使存储器被使用或不被使用。 由于串行访问存储器执行连续数据写入和读取，所以可以实现高速访问，从而可以以大的存储容量廉价地制造。 因此，可以增加CPU中的处理速度，而可以廉价地制造并行算术逻辑处理装置。

公开(公告)号：US5023710A

公开(公告)日：1991-06-11

申请号：US602477

申请日：1990-10-24

申请人： Tetsujiro Kondo ,  Michio Nagai ,  Norihisa Shirota

发明人： Tetsujiro Kondo ,  Michio Nagai ,  Norihisa Shirota

IPC分类号： H04N5/92 ,  H03M7/30 ,  H03M7/40 ,  H04N5/783 ,  H04N5/926 ,  H04N19/00 ,  H04N19/115 ,  H04N19/13 ,  H04N19/132 ,  H04N19/136 ,  H04N19/137 ,  H04N19/149 ,  H04N19/176 ,  H04N19/186 ,  H04N19/196 ,  H04N19/423 ,  H04N19/46 ,  H04N19/587 ,  H04N19/59 ,  H04N19/60 ,  H04N19/65 ,  H04N19/66 ,  H04N19/70 ,  H04N19/85 ,  H04N19/89 ,  H04N19/895 ,  H04N19/91 ,  H04N19/98

CPC分类号： H04N5/9261 ,  H04N19/89 ,  H04N19/98 ,  H04N5/783

摘要： A highly efficient coding apparatus is configured to divide a digital picture signal into picture blocks and, based on a signal from a coding circuit for performing variable-length coding of each picture block, generate an output signal in the form of serial sync blocks. By inserting the most significant bit of a coded output signal for each picture element in a predetermined position of each sync block, a reproduced picture is obtained in a picture search mode in which a magnetic head scans a video tape across a plurality of tracks.

公开(公告)号：US4677499A

公开(公告)日：1987-06-30

申请号：US721658

申请日：1985-04-10

申请人： Norihisa Shirota ,  Takao Yamazaki ,  Seiichiro Iwase

发明人： Norihisa Shirota ,  Takao Yamazaki ,  Seiichiro Iwase

IPC分类号： G11B20/10 ,  A63F7/02 ,  G11B20/18 ,  H03K5/00 ,  H03K5/13 ,  H04N5/92 ,  H04N5/95 ,  H03K5/14

CPC分类号： H03K5/131 ,  G11B20/18 ,  H04N5/95 ,  H03K2005/00241

摘要： There is provided a digital time base corrector in which a digital input signal of one block consisting of a continuous data time sequence is converted to a digital signal including data lack intervals or vice versa by a variable delay circuit. A signal selecting circuit is divided into N first unit selecting circuits and a second unit selecting circuit. M of the output signals of a shift register are inputted to the first unit selecting circuits, by which one of them is selected. The outputs of the N first unit selecting circuits are supplied to the second unit selecting circuit, by which one of them is selected. A pipeline process is performed by inserting a delay circuit to delay the signal for the time of one clock period into the input/output line of the second unit selecting circuit. Further, the selecting signal can be made variable for every one clock and a delay circuit is inserted on the output side of a selecting signal forming circuit. With this corrector, the influence of the gate delay of the selectors can be reduced and the high speed data process can be performed.

摘要翻译： 提供了一种数字时基校正器，其中由连续数据时间序列组成的一个块的数字输入信号通过可变延迟电路被转换为包括数据缺少间隔或反之亦然的数字信号。 信号选择电路被分为N个第一单元选择电路和第二单元选择电路。 移位寄存器的输出信号的M被输入到第一单元选择电路，通过它们中的一个被选择。 N个第一单位选择电路的输出被提供给第二单元选择电路，由此选择其中一个。 通过插入延迟电路来执行一个时钟周期时间的信号到第二单元选择电路的输入/输出线中的流水线处理。 此外，可以使选择信号每一个时钟变化，并且在选择信号形成电路的输出侧插入延迟电路。 利用该校正器，可以减小选择器的门延迟的影响，并且可以执行高速数据处理。

公开(公告)号：US4345272A

公开(公告)日：1982-08-17

申请号：US192367

申请日：1980-09-30

申请人： Norihisa Shirota

发明人： Norihisa Shirota

IPC分类号： H04N9/88 ,  H04N9/888 ,  H04N9/535

CPC分类号： H04N9/888

摘要： In an apparatus for processing a color video signal including luminance and chrominance components and composed of successive frames each having a plurality of fields constituted by successive lines which are interlaced in a pictorial representation of a complete frame, a memory is provided to have the received video signal written therein at an address at which there was earlier written the video signal of a line of the next previous field which, in the pictorial representation of the complete frame, is positioned immediately adjacent the line of the video signal being received. An error in the received video signal is detected and, in response thereto, the writing of the error-containing video signal in the memory is inhibited and the error-free video signal previously written at the corresponding address is read out, with the chrominance component of the readout signal being phase inverted and added to the luminance component of the read-out signal so as to provide a color video signal which can replace and conceal the error-containing signal.

摘要翻译： 在用于处理包括亮度和色度分量并由连续帧组成的彩色视频信号的装置中，每个帧具有由完整帧的图形表示中的隔行扫描构成的多个场构成的存储器，以提供接收到的视频 信号写入其中较早地址的地址，其中写入下一个前一场的行的视频信号，其在完整帧的图形表示中紧邻正在接收的视频信号的行。 检测到接收到的视频信号中的错误，并且响应于此，禁止在存储器中写入含错误的视频信号，并且读出先前写入相应地址的无错误视频信号，其中色度分量 的读出信号被相位反相并且被加到读出信号的亮度分量中，以便提供一种彩色视频信号，该彩色视频信号可以代替和隐藏含错误信号。

公开(公告)号：US5006931A

公开(公告)日：1991-04-09

申请号：US482252

申请日：1990-02-20

申请人： Norihisa Shirota

发明人： Norihisa Shirota

IPC分类号： H04N1/415 ,  H04N19/124 ,  H04N19/126 ,  H04N19/132 ,  H04N19/134 ,  H04N19/136 ,  H04N19/146 ,  H04N19/172 ,  H04N19/176 ,  H04N19/186 ,  H04N19/196 ,  H04N19/42 ,  H04N19/423 ,  H04N19/46 ,  H04N19/59 ,  H04N19/60 ,  H04N19/625 ,  H04N19/65 ,  H04N19/70

CPC分类号： H04N19/192 ,  H04N19/115 ,  H04N19/126 ,  H04N19/14 ,  H04N19/149 ,  H04N19/176 ,  H04N19/60 ,  H04N19/61 ,  H04N19/124 ,  H04N19/146 ,  H04N19/152

摘要： A highly efficient coding apparatus for encoding digital video data in a block format and compressing the video data if required into a number of bits so that the total number of bits in the digital video data to be transmitted is less than that of a predetermined transmission capacity. Coefficient data having a DC component and a plurality of AC components for each block are generated by an orthogonal transformation. A distribution table of the AC coefficient data is generated during a predetermined period, and an accumulating distribution table is generated from the distribution table. The total bit number of the AC coefficient data generated during the predetermined period is controlled in response to the accumulating distribution table and the predetermined transmission capacity of the data transmission channel. The DC coefficient data, the controlled AC coefficient data and an additional code are transmitting for each of the predetermined periods.

公开(公告)号：US4697248A

公开(公告)日：1987-09-29

申请号：US685125

申请日：1984-12-21

申请人： Norihisa Shirota

发明人： Norihisa Shirota

IPC分类号： G06F11/10 ,  G06F7/72 ,  H03M13/00 ,  H03M13/03 ,  H03M13/15 ,  G06F7/52

CPC分类号： G06F7/724 ,  H03M13/033 ,  H03M13/151

摘要： In an arithmetic circuit, a first input of m bits representing the vector expression of a first set of elements of a finite field GF(2m) is converted into the components of a matrix, and each component of the matrix is multiplied by second input of m bits representing the vector expression of a second set of elements of the finite field. A vector product of the first and second inputs is thereby obtained.

摘要翻译： 在算术电路中，表示有限域GF（2m）的第一组元素的向量表达式的m位的第一输入被转换为矩阵的分量，并且矩阵的每个分量乘以 m位表示有限域的第二组元素的向量表达式。 从而获得第一和第二输入的向量积。