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    Method of manufacturing mask and method of manufacturing semiconductor integrated circuit device
    1.
    发明授权
    Method of manufacturing mask and method of manufacturing semiconductor integrated circuit device 有权
    半导体集成电路器件的制造方法和半导体集成电路器件的制造方法

    公开(公告)号：US06841399B2

    公开(公告)日：2005-01-11

    申请号：US10349026

    申请日：2003-01-23

    申请人： Norio Hasegawa ,  Katsuya Hayano ,  Shinji Kubo ,  Yasuhiro Koizumi ,  Hironobu Takaya ,  Morihisa Hoga

    发明人： Norio Hasegawa ,  Katsuya Hayano ,  Shinji Kubo ,  Yasuhiro Koizumi ,  Hironobu Takaya ,  Morihisa Hoga

    IPC分类号： G03F1/50 ,  G03F1/56 ,  G03F1/62 ,  G03F1/72 ,  G03F1/84 ,  G03F7/20 ,  H01L21/027 ,  H01L21/00

    CPC分类号： G03F1/84 ,  G03F1/56 ,  Y10S438/949

    摘要： The manufacturing time of a mask is shortened. In a defect inspection of a mask having a light-shielding portion composed of a resist film, the presence or absence of defects, such as burr and film loss of a resist pattern on the mask, and foreign matters, etc. is inspected by reading optical information on either or both of reflection light and transmission light with respect to inspection light irradiated to the mask by the use of a foreign-matter inspection system. More specifically, in the inspection of the mask, it is possible to perform the defect inspection without performing a comparison inspection that requires a great amount of measuring time and advanced techniques. Therefore, the inspecting process of the mask can be simplified, and also the inspecting time of the mask can be shortened.

    摘要翻译： 掩模的制造时间缩短。 在具有由抗蚀剂膜构成的遮光部的掩模的缺陷检查中，通过读取检查有无缺陷，例如掩模上的抗蚀剂图案的毛刺和膜损失以及异物等 相对于通过使用异物检查系统照射到面罩的检查光，反射光和透射光中的任一个或两者的光学信息。 更具体地，在掩模的检查中，可以进行缺陷检查，而不进行需要大量测量时间和先进技术的比较检查。 因此，可以简化掩模的检查过程，并且可以缩短掩模的检查时间。

    Fabrication method of semiconductor integrated circuit device and mask fabrication method
    2.
    发明授权
    Fabrication method of semiconductor integrated circuit device and mask fabrication method 有权
    半导体集成电路器件的制造方法和掩模制造方法

    公开(公告)号：US07252910B2

    公开(公告)日：2007-08-07

    申请号：US10762548

    申请日：2004-01-23

    申请人： Norio Hasegawa ,  Katsuya Hayano ,  Shinji Kubo ,  Yasuhiro Koizumi ,  Yasushi Kawai

    发明人： Norio Hasegawa ,  Katsuya Hayano ,  Shinji Kubo ,  Yasuhiro Koizumi ,  Yasushi Kawai

    IPC分类号： G03F1/00

    CPC分类号： G03F1/72 ,  G03F1/64

    摘要： A mask fabrication time is shortened. By patterning an electron-sensitive resist film coated on a main surface of a mask substrate, a pellicle is mounted on the main surface of the mask substrate immediately after a resist pattern made from an electron beam sensitive resist film and having light-shielding characteristics with respect to exposure light is formed. Subsequently, by irradiating a laser beam to defect made from the electron beam sensitive resist film with the pellicle being mounted on the mask substrate, the defect is removed. Since the defect can be removed without removing the pellicle, the mask fabrication time can be shortened.

    摘要翻译： 掩模制造时间缩短。 通过对涂布在掩模基板的主表面上的电子敏感膜形成图案，将防护薄膜组件立即安装在掩模基板的主表面上，紧接在由电子束敏感抗蚀剂膜制成的抗蚀剂图案之后，具有遮光特性 形成曝光光。 随后，通过将光束照射到由防护薄膜组件安装在掩模基板上的由电子束敏感抗蚀剂膜制成的缺陷上，从而去除缺陷。 由于可以在不去除防护薄膜的情况下去除缺陷，因此可以缩短掩模制造时间。

    Method of manufacturing semiconductor integrated circuit devices
    4.
    发明授权
    Method of manufacturing semiconductor integrated circuit devices 失效
    制造半导体集成电路器件的方法

    公开(公告)号：US07172853B2

    公开(公告)日：2007-02-06

    申请号：US10770413

    申请日：2004-02-04

    申请人： Norio Hasegawa ,  Akira Imai ,  Katsuya Hayano

    发明人： Norio Hasegawa ,  Akira Imai ,  Katsuya Hayano

    IPC分类号： G03F7/20 ,  G03C5/00

    CPC分类号： G03F7/70358 ,  G03F1/30 ,  G03F7/70283 ,  G03F7/70466

    摘要： To alleviate the absolute value control accuracy of phases in a mask having a groove shifter structure, transfer regions formed at different planar positions on the same plane of the same mask are subjected to a multiple exposure by scanning exposure. Although identical mask patterns are formed over the transfer regions respective groove shifters provided to these mask patterns are arranged opposite from each other.

    摘要翻译： 为了减轻具有凹槽移位结构的掩模中的相位的绝对值控制精度，形成在同一掩模的同一平面上的不同平面位置处的转印区域通过扫描曝光进行多次曝光。 虽然在传送区域上形成相同的掩模图案，但是设置在这些掩模图案上的相应凹槽移位器相互排列。

    Manufacturing method of semiconductor integrated circuit devices and mask manufacturing methods
    5.
    发明授权
    Manufacturing method of semiconductor integrated circuit devices and mask manufacturing methods 失效
    半导体集成电路器件的制造方法和掩模制造方法

    公开(公告)号：US06548312B1

    公开(公告)日：2003-04-15

    申请号：US09640721

    申请日：2000-08-18

    申请人： Katsuya Hayano ,  Norio Hasegawa ,  Akira Imai ,  Naoko Asai ,  Eiji Tsujimoto ,  Takahiro Watanabe

    发明人： Katsuya Hayano ,  Norio Hasegawa ,  Akira Imai ,  Naoko Asai ,  Eiji Tsujimoto ,  Takahiro Watanabe

    IPC分类号： H01L2100

    CPC分类号： G03F7/70433

    摘要： In order to inhibit or prevent a pattern abnormality such as the deformation or misalignment of a pattern of a semiconductor integrated circuit device, a light intensity is calculated based on the pattern data DBP of a mask and the aberration data DBL of a lens of a pattern exposure device (step 101) and then the results of the light intensity calculation is compared with the results of the light intensity calculated on condition that the lens of the pattern exposure device has no aberration (step 102), and then a pattern data exceeding an allowable level, of the pattern data of the mask, is corrected according to the amount of correction calculated on the basis of the results of the comparison such that the pattern data does not exceed the allowable level (step 104). The mask is manufactured by using the mask making data DBM after the correction and then is mounted on the pattern exposure device to transfer a predetermined pattern to a semiconductor wafer.

    摘要翻译： 为了抑制或防止诸如半导体集成电路器件的图案的变形或未对准的图案异常，基于掩模的图案数据DBP和图案的透镜的像差数据DBL计算光强度 曝光装置（步骤101），然后将光强度计算的结果与在图案曝光装置的透镜没有像差的条件下计算的光强度的结果进行比较（步骤102），然后模式数据超过 根据比较结果计算出的校正量，使图案数据不超过允许值（步骤104），对掩模的图案数据的允许电平进行校正。 通过在校正后使用掩模制作数据DBM来制造掩模，然后安装在图案曝光装置上以将预定图案转印到半导体晶片。

    Method of manufacturing a semiconductor device
    7.
    发明申请
    Method of manufacturing a semiconductor device 审中-公开
    制造半导体器件的方法

    公开(公告)号：US20050277065A1

    公开(公告)日：2005-12-15

    申请号：US11147222

    申请日：2005-06-08

    申请人： Norio Hasegawa ,  Katsuya Hayano

    发明人： Norio Hasegawa ,  Katsuya Hayano

    IPC分类号： G03F1/54 ,  G03F1/56 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/8238 ,  H01L27/092

    CPC分类号： G03F1/34 ,  G03F1/29 ,  G03F1/56

    摘要： By using a high-accuracy mask capable of being manufactured through a simplified step, a semiconductor device manufacturing method of forming a desired pattern over a wafer is provided. A relatively narrow groove pattern and a groove pattern wider than the narrow groove pattern are formed, and a shade film made of, for example, a resist film is formed in the relatively wide groove pattern. As a concrete method of manufacturing a mask, after applying a resist film onto the quartz glass substrate, exposure and developing processings are performed, whereby the resist film is patterned. The patterned resist film is used as a mask to form the groove patterns in the quartz glass substrate (dry etching). Subsequently, after removing the patterned resist film, a new resist film is applied. Then, patterning is performed to form the shade film only in the groove pattern.

    摘要翻译： 通过使用能够通过简化步骤制造的高精度掩模，提供了在晶片上形成期望图案的半导体器件制造方法。 形成比窄槽图案宽的相对窄的槽图案和凹槽图案，并且以比较宽的凹槽图案形成由例如抗蚀剂膜制成的遮光膜。 作为制造掩模的具体方法，在将石英玻璃基板上施加抗蚀剂膜之后，进行曝光和显影处理，从而对抗蚀剂膜进行图案化。 图案化的抗蚀剂膜用作掩模以在石英玻璃基板（干蚀刻）中形成凹槽图案。 随后，在去除图案化的抗蚀剂膜之后，施加新的抗蚀剂膜。 然后，进行图案化以仅在凹槽图案中形成遮光膜。

    Manufacturing method of semiconductor integrated circuit device
    9.
    发明申请
    Manufacturing method of semiconductor integrated circuit device 失效
    半导体集成电路器件的制造方法

    公开(公告)号：US20050090120A1

    公开(公告)日：2005-04-28

    申请号：US10967277

    申请日：2004-10-19

    申请人： Norio Hasegawa ,  Katsuya Hayano ,  Shoji Hotta

    发明人： Norio Hasegawa ,  Katsuya Hayano ,  Shoji Hotta

    IPC分类号： G03C5/00 ,  G03F1/30 ,  G03F1/32 ,  G03F1/68 ,  G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/311 ,  H01L21/768

    CPC分类号： H01L21/76808 ,  G03F1/30 ,  G03F1/32 ,  G03F1/50 ,  H01L21/31144

    摘要： In a massed region of each of a plurality of transfer areas of a mask a plurality of light transmission patterns are formed by opening a half-tone film. A phase shifter is disposed in each of the light transmission patterns so that a 180° phase inversion occurs between the lights that transmit through adjacent light transmission patterns. In a sparse region of the plurality of transfer areas a solitary light transmission pattern is formed by opening the half-tone film. Both shape and size are the same among the light transmission patterns, which are disposed symmetrically in both the massed and sparse regions about the center between the transfer areas. The phase shifters in the massed regions are disposed so that the phase of each phase shifter in one of the transfer areas comes to be opposed to that of its counterpart in the other transfer area. In the exposure process, those transfer areas are overlaid one upon another in the same chip region.

    摘要翻译： 在掩模的多个转印区域的每一个的质量区域中，通过打开半色调膜形成多个透光图案。 在每个透光图案中设置移相器，使得在通过相邻光传输图案传输的光之间发生180°的相位反转。 在多个转印区域的稀疏区域中，通过打开半色调膜形成单独的透光图案。 在透光图案之间的形状和尺寸都相同，所述光透射图案在转印区域之间的中心周围的质量和稀疏区域中对称地设置。 配置区域中的移相器被布置成使得其中一个传送区域中的每个移相器的相位与其它传送区域中的相应部件的相位相反。 在曝光处理中，这些传送区域在相同的芯片区域中彼此重叠。

    Method of manufacturing photomask and method of manufacturing semiconductor integrated circuit device
    10.
    发明授权
    Method of manufacturing photomask and method of manufacturing semiconductor integrated circuit device 失效
    制造光掩模的方法和制造半导体集成电路器件的方法

    公开(公告)号：US06824958B2

    公开(公告)日：2004-11-30

    申请号：US10025457

    申请日：2001-12-26

    申请人： Katsuya Hayano ,  Norio Hasegawa

    发明人： Katsuya Hayano ,  Norio Hasegawa

    IPC分类号： G03C500

    CPC分类号： G03F3/10 ,  G03F1/26

    摘要： Disclosed is a technique capable of reducing the manufacturing time of a photomask. In a method of transferring a predetermined pattern onto a semiconductor wafer by reduced projection exposure using a product mask manufactured by performing the reduced projection exposure to a pattern of an IP mask Mm1, the IP mask Mm1 is designed to have a resist mask structure in which a light-shielding pattern thereof is constituted of an organic film such as a resist film.

    摘要翻译： 公开了能够减少光掩模的制造时间的技术。 在通过使用通过对IP掩模Mm1的图案执行减少的投影曝光制造的产品掩模的减少的投影曝光将预定图案转印到半导体晶片上的方法中，IP掩模Mm1被设计为具有抗蚀剂掩模结构，其中 其遮光图案由诸如抗蚀剂膜的有机膜构成。