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    High-resolution lithography and semiconductor device manufacturing method
    4.
    发明授权
    High-resolution lithography and semiconductor device manufacturing method 失效
    高分辨率光刻和半导体器件制造方法

    公开(公告)号：US5350485A

    公开(公告)日：1994-09-27

    申请号：US9012

    申请日：1993-01-26

    Applicant: Hiroshi Shiraishi ,  Takashi Soga ,  Fumio Murai ,  Toshio Sakamizu ,  Nobuaki Hayashi

    Inventor： Hiroshi Shiraishi ,  Takashi Soga ,  Fumio Murai ,  Toshio Sakamizu ,  Nobuaki Hayashi

    IPC: G03F7/038 ,  G03F7/039 ,  G03F7/26 ,  G03F7/38 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/00

    CPC classification number: G03F7/26 ,  G03F7/38 ,  H01L21/0277 ,  H01L21/0278 ,  H01L21/32139

    Abstract: A lithographic method for forming a mask pattern is useful for etching wiring or insulator layers on a substrate. A catalyst generation layer and a latent image formation layer are formed on the target layer prior to application of actinic radiation to activate a catalyst in the catalyst generation layer in accordance with a predetermined pattern. The activated catalyst diffuses into the latent image formation layer to form a latent image, which then serves as a mask pattern for etching the catalyst generation layer, latent image formation layer and target layer. The catalyst generation layer may be formed prior to the latent image formation layer, or vice versa. In another embodiment, the catalyst generation layer is formed prior to the radiation step, but the latent image formation layer is formed after application of the actinic radiation.

    Abstract translation: 用于形成掩模图案的光刻方法对于蚀刻衬底上的布线或绝缘体层是有用的。 在施加光化辐射之前，在靶层上形成催化剂生成层和潜像形成层，以根据预定图案活化催化剂生成层中的催化剂。 活化的催化剂扩散到潜像形成层中以形成潜像，然后用作蚀刻催化剂生成层，潜像形成层和目标层的掩模图案。 催化剂生成层可以在潜像形成层之前形成，反之亦然。 在另一个实施方案中，在辐射步骤之前形成催化剂生成层，但是在施加光化辐射之后形成潜像形成层。

    Photomask and method for manufacturing semiconductor device using photomask
    5.
    发明授权
    Photomask and method for manufacturing semiconductor device using photomask 失效
    光掩模和使用光掩模制造半导体器件的方法

    公开(公告)号：US5318868A

    公开(公告)日：1994-06-07

    申请号：US883532

    申请日：1992-05-15

    Applicant: Norio Hasegawa ,  Fumio Murai

    Inventor： Norio Hasegawa ,  Fumio Murai

    IPC: G03F1/30 ,  G03F1/32 ,  G03F1/34 ,  G03F1/68 ,  G03F7/20 ,  H01L21/027 ,  H01L21/30 ,  G03F9/00

    CPC classification number: G03F1/26 ,  G03F1/32 ,  G03F7/70466 ,  G03F7/70475

    Abstract: A photomask which is suitable for a phase shift method and a method for manufacturing a semiconductor device using the photomask is disclosed. The photomask comprises a transparent area, a translucent area and an opaque are arranged in a particular manner relative to a shifter film. In particular, the different elements are arranged so that the lowering of intensity and the amplitude of a transmitted light in the transparent area caused by an unnecessary peripheral part of a shifter film are smaller than the lowering of the intensity and the amplitude of a transmitted light through a transparent area. This serves to prevent an undesirable influence of the unnecessary peripheral part of so that a shifter film can reading be prevented, and a connected pattern can be formed.

    Abstract translation: 公开了适用于相移方法的光掩模和使用光掩模的半导体器件的制造方法。 光掩模包括透明区域，半透明区域和不透明区域，以相对于移位膜的特定方式布置。 特别地，不同的元件被布置成使得由移位膜的不必要的周边部分引起的在透明区域中的透射光的强度和振幅的降低小于透射光的强度和振幅的降低 通过透明区域。 这用于防止不必要的周边部分的不期望的影响，从而防止移位膜读取，并且可以形成连接的图案。

    Pattern fabrication method using a charged particle beam and apparatus for realizing same
    7.
    发明授权
    Pattern fabrication method using a charged particle beam and apparatus for realizing same 失效
    使用带电粒子束的图案制造方法及其实现装置

    公开(公告)号：US5149975A

    公开(公告)日：1992-09-22

    申请号：US647562

    申请日：1991-01-29

    Applicant: Haruo Yoda ,  Fumio Murai

    Inventor： Haruo Yoda ,  Fumio Murai

    IPC: G03F7/20 ,  H01J37/302 ,  H01L21/027 ,  H01L21/30

    CPC classification number: H01J37/3026 ,  H01J2237/31769

    Abstract: The present application relates to a method and an apparatus for forming a pattern, in which a plane on which a pattern on a sample is traced is decomposed into predetermined partial regions; the pattern density in each of the partial regions is stored in data storing means as pattern density map data; and the irradiation energy amount of a charged particle beam is corrected on the basis of the pattern density map data to correct shortage and excess in the exposure dose due to roughness and fineness of the the pattern, i.e. the proximity effect. Further, the present application relates to a method and an apparatus for forming a pattern, in which when one or a plurality of layers located under the layer on which the pattern should be formed have patterns, influences of the underlayers on the proximity effect are taken into account.

    Abstract translation: 本申请涉及一种用于形成图案的方法和装置，其中将跟踪样本上的图案的平面分解成预定的部分区域; 每个部分区域中的图案密度作为图案密度图数据存储在数据存储装置中; 并且基于图案密度图数据校正带电粒子束的照射能量，以校正由于图案的粗糙度和细度，即邻近效应引起的曝光剂量的不足和过剩。 此外，本申请涉及用于形成图案的方法和装置，其中当位于其上应形成图案的层下面的一个或多个层具有图案时，取下底层对邻近效应的影响 考虑到

    Semiconductor device and a manufacturing method of the same
    8.
    发明授权
    Semiconductor device and a manufacturing method of the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06709880B2

    公开(公告)日：2004-03-23

    申请号：US10171769

    申请日：2002-06-17

    Applicant: Jiro Yamamoto ,  Fumio Murai ,  Tsuneo Terasawa ,  Tosiyuki Yamamoto

    Inventor： Jiro Yamamoto ,  Fumio Murai ,  Tsuneo Terasawa ,  Tosiyuki Yamamoto

    IPC: H01L2100

    CPC classification number: B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  H01J37/3174 ,  H01J2237/31757

    Abstract: There is disclosed a method for forming micro patterns in a semiconductor integrated circuit device with high productivity and high accuracy. A photolithography having high throughput and electron beam lithography using a reticle and having relatively high throughput and high resolution are selectively used so as to obtain highest throughput while satisfying accuracy and resolution required for each product/layer. In the case of using the electron beam lithography, a non-complementary reticle and a complementary reticle are selectively used so as to obtain highest throughput while satisfying required accuracy and resolution. Thus, productivity and integration can be improved for the semiconductor integrated circuit device.

    Abstract translation: 公开了一种以高生产率和高精度在半导体集成电路器件中形成微图案的方法。 选择性地使用具有高通量和使用掩模版并且具有相对高的通量和高分辨率的电子束光刻的光刻，以便在满足每个产品/层所需的精度和分辨率的同时获得最高的吞吐量。 在使用电子束光刻的情况下，选择性地使用非互补掩模版和互补掩模版，以便在满足所需精度和分辨率的同时获得最高的吞吐量。 因此，可以提高半导体集成电路器件的生产率和集成度。

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