公开(公告)号：US20230041794A1

公开(公告)日：2023-02-09

申请号：US17809480

申请日：2022-06-28

Applicant: Novellus Systems, Inc.

Inventor： Anand CHANDRASHEKAR ,  Esther JENG ,  Raashina Humayun ,  Michal DANEK ,  Juwen GAO ,  Deqi WANG

IPC: H01L21/768 ,  H01L27/108 ,  C23C16/04 ,  C23C16/06 ,  H01L21/285 ,  H01L21/321

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

公开(公告)号：US20210327754A1

公开(公告)日：2021-10-21

申请号：US17359068

申请日：2021-06-25

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/768 ,  H01L21/285 ,  H01L27/105 ,  H01L27/108 ,  C23C16/04 ,  H01L21/3213

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

公开(公告)号：US11075115B2

公开(公告)日：2021-07-27

申请号：US16124050

申请日：2018-09-06

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/768 ,  H01L21/285 ,  H01L27/105 ,  H01L27/108 ,  C23C16/04 ,  H01L21/3213 ,  H01L21/321

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

公开(公告)号：US20190019725A1

公开(公告)日：2019-01-17

申请号：US16124050

申请日：2018-09-06

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/768 ,  H01L27/108 ,  C23C16/04 ,  H01L27/105 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/321

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

公开(公告)号：US09589835B2

公开(公告)日：2017-03-07

申请号：US13934089

申请日：2013-07-02

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Raashina Humayun

IPC: H01L21/44 ,  H01L21/768 ,  C23C16/14 ,  C23C16/56 ,  H01L21/285

CPC classification number: H01L21/76838 ,  C23C16/14 ,  C23C16/56 ,  H01L21/28556

Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.

Abstract translation: 提供了增加钨膜的反射率以形成具有高反射率，低电阻率和低粗糙度的膜的自顶向下的方法。 这些方法涉及钨的大量沉积，然后除去沉积的钨的顶部。 在特定实施例中，去除沉积的钨的顶部部分包括使其暴露于含氟等离子体。 该方法产生具有较低粗糙度和较高反射率的低电阻率钨体层。 与常规的低电阻率钨膜相比，光滑和高反射性的钨层比光图案更容易。 应用包括形成钨线。

公开(公告)号：US20160190008A1

公开(公告)日：2016-06-30

申请号：US14965806

申请日：2015-12-10

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/32136 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76898 ,  H01L27/1052 ,  H01L27/10891

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

公开(公告)号：US08835317B2

公开(公告)日：2014-09-16

申请号：US13888077

申请日：2013-05-06

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Raashina Humayun ,  Michal Danek ,  Aaron R. Fellis ,  Sean Chang

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213

CPC classification number: H01L21/486 ,  H01L21/28556 ,  H01L21/32136 ,  H01L21/76865 ,  H01L21/76877

Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.

Abstract translation: 提供了以基本上无空隙的方式用含钨材料填充高纵横比特征的方法和装置。 在某些实施方案中，该方法包括沉积含钨材料的初始层，然后选择性地去除初始层的一部分以形成沿着高纵横比特征的深度差异钝化的剩余层。 在某些实施例中，剩余层在特征开口附近比在特征内更加钝化。 该方法可以继续在剩余层上沉积相同或其它材料的附加层。 由于剩余层的差分钝化，在该后续沉积操作期间的沉积速率在特征开口附近比在特征内部的沉积速率更慢。 这种沉积变化又可以有助于防止特征的过早闭合并且有助于以基本无空隙的方式填充特征。

公开(公告)号：US08809161B2

公开(公告)日：2014-08-19

申请号：US13935398

申请日：2013-07-03

Applicant: Novellus Systems, Inc.

Inventor： Vishal Gauri ,  Raashina Humayun ,  Chi-I Lang ,  Judy H. Huang ,  Michael Barnes ,  Sunil Shanker

IPC: H01L21/4757

CPC classification number: H01L21/31 ,  C23C16/045 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0234 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/31608 ,  H01L21/76224

Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.

Abstract translation: 本发明的方法涉及通过在间隙中形成可流动的膜来填充具有固体电介质材料的衬底上的间隙。 可流动膜提供一致的，无空隙的间隙填充。 然后将膜转化成固体电介质材料。 以这种方式，用固体电介质材料填充衬底上的间隙。 根据各种实施方案，所述方法包括使电介质前体与氧化剂反应以形成电介质材料。 在某些实施方案中，电介质前体冷凝并随后与氧化剂反应以形成电介质材料。 在某些实施方案中，气相反应物反应形成冷凝的可流动的膜。

公开(公告)号：US20190206731A1

公开(公告)日：2019-07-04

申请号：US16294736

申请日：2019-03-06

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/768 ,  C23C16/06 ,  C23C16/04 ,  H01L21/285 ,  H01L21/321 ,  H01L27/108

CPC classification number: H01L21/76879 ,  C23C16/04 ,  C23C16/045 ,  C23C16/06 ,  H01L21/28556 ,  H01L21/321 ,  H01L21/76898 ,  H01L27/10891

Abstract: Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

公开(公告)号：US10103058B2

公开(公告)日：2018-10-16

申请号：US15482271

申请日：2017-04-07

Applicant: Novellus Systems, Inc.

Inventor： Anand Chandrashekar ,  Esther Jeng ,  Raashina Humayun ,  Michal Danek ,  Juwen Gao ,  Deqi Wang

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/3213 ,  C23C16/04 ,  H01L27/108 ,  H01L27/105 ,  H01L21/285 ,  H01L21/321

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).