公开(公告)号：US09479001B2

公开(公告)日：2016-10-25

申请号：US14011635

申请日：2013-08-27

Applicant: NVIDIA CORPORATION

Inventor： Rene Marchand ,  Thomas Dean Skelton ,  Matthew Longnecker ,  Brian Smith

IPC: G05F1/56 ,  H02J7/00 ,  G06F1/00

CPC classification number: H02J7/0063 ,  G05F1/56 ,  G06F1/00 ,  G06F1/263 ,  G06F1/28

Abstract: A regulator draws power from a battery or power delivery system and supplies regulated power to a load according to alternating modes of operation. In a voltage control mode, the regulator supplies power with a nominal voltage level and a fluctuating current level that is allowed to float according to the current demands of the load. When the load demands an amount of current that could potentially cause damage, the regulator transitions to a current control mode. In the current control mode, the regulator supplies power with a fluctuating voltage level and a maximum current level. The regulator transitions between voltage control mode and current control mode in order to supply a maximum power level to the load without exceeding the maximum current level. The regulator is also configured to limit the power drawn from the battery by decreasing the maximum output current, potentially avoiding voltage droop.

Abstract translation: 调节器从电池或电力输送系统获取电力，并根据交替工作模式向负载供电。 在电压控制模式下，稳压器根据负载的当前需求，提供额定电压电平和允许浮动的波动电流电平的电源。 当负载需要可能导致损坏的电流量时，调节器转换到当前控制模式。 在电流控制模式下，稳压器以波动的电压电平和最大电流电平供电。 调节器在电压控制模式和电流控制模式之间转换，以便在不超过最大电流电平的情况下向负载提供最大功率电平。 调节器还被配置为通过减小最大输出电流来限制从电池抽取的功率，潜在地避免电压下降。

公开(公告)号：US20150212149A1

公开(公告)日：2015-07-30

申请号：US14163066

申请日：2014-01-24

Applicant: Nvidia Corporation

Inventor： Brian Smith ,  Stephen Felix ,  Tezaswi Raja ,  Roman Surgutchik

IPC: G01R31/28 ,  G01R1/30

CPC classification number: G01R31/2858 ,  G01R1/30 ,  G01R31/2837 ,  G01R31/2851 ,  G01R31/31727 ,  H03K3/0315

Abstract: A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

Abstract translation: 用于集成电路（IC）的劣化检测器，检测IC中的老化的方法和结合了劣化检测器的IC或方法。 在一个实施例中，劣化检测器包括：（1）耦合到功率门和时钟门的离线环形振荡器（RO），（2）耦合到时钟门的冷冻RO，（3）在线RO和（4） ）分析器，其耦合到离线RO，冷冻RO和在线RO，并且可操作以将劣化检测器置于正常状态，其中脱机RO与驱动电压源和时钟源两者断开，冷冻RO连接 到驱动电压源但与时钟源断开，并且在线RO连接到驱动电压源和时钟源。

公开(公告)号：US11276648B2

公开(公告)日：2022-03-15

申请号：US16051315

申请日：2018-07-31

Applicant: Nvidia Corporation

Inventor： Chinmay Apte ,  Brian Smith ,  Tezaswi Raja ,  Roman Surgutchik

IPC: H01L23/552 ,  H01L23/00 ,  G06F21/75 ,  H02H9/04 ,  H01L23/66 ,  G06F21/87

Abstract: An on-chip electromagnetic (EM) pulse protection circuit detects EM pulse attacks, generates an alarm, and performs a defensive action to protect the integrated circuit. The EM pulse protection circuit can be used with various integrated circuits or manufactured chips in which, for example, there is a desire to keep information secure, maintain the security of the chip, secure boot processes, and/or protect private keys.

公开(公告)号：US20200043868A1

公开(公告)日：2020-02-06

申请号：US16051315

申请日：2018-07-31

Applicant: Nvidia Corporation

Inventor： Chinmay Apte ,  Brian Smith ,  Tezaswi Raja ,  Roman Surgutchik

IPC: H01L23/00 ,  H01L23/552 ,  G06F21/75 ,  H01L23/66 ,  G06F21/87

Abstract: This disclosure relates to detecting and responding to electromagnetic (EM) pulse attacks on integrated circuits. As such, the disclosure provides an on-chip EM pulse protection circuit that detects EM pulse attacks, generates an alarm in response thereof, and performs a defensive action to protect the integrated circuit. The EM pulse protection circuit can be used with various integrated circuits or manufactured chips in which, for example, there is a desire to keep information secure, maintain the security of the chip, secure boot processes, and/or protect private keys.

公开(公告)号：US12032840B2

公开(公告)日：2024-07-09

申请号：US17678784

申请日：2022-02-23

Applicant: NVIDIA CORPORATION

Inventor： Anand Shanmugam Sundararajan ,  Narayan Kulshrestha ,  Ka Yun Lee ,  Brian Smith ,  Madhukiran V. Swarna ,  Ramachandiran V ,  Kevin Wilder

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0673

Abstract: Various embodiments include a computer memory system that dynamically adjusts a memory device performance feature, such as dynamic assist control, dynamic turbo mode, and/or the like, to improve the performance of memory devices in the memory system. The memory system enables or disables the memory device performance feature based on the operating voltage relative to a threshold voltage. If the operating voltage crosses the threshold voltage in one direction, then the memory device system enables the memory device performance feature. If the operating voltage crosses the threshold voltage in another direction, then the memory system disables the memory device performance feature. Various techniques enable the memory device performance feature to be employed even with complex integrated circuits that may include tens of thousands of devices that employ the memory device performance feature.

公开(公告)号：US09494641B2

公开(公告)日：2016-11-15

申请号：US14163066

申请日：2014-01-24

Applicant: Nvidia Corporation

Inventor： Brian Smith ,  Stephen Felix ,  Tezaswi Raja ,  Roman Surgutchik

IPC: G01R31/28 ,  G01R31/317 ,  H03K3/03 ,  G01R1/30

CPC classification number: G01R31/2858 ,  G01R1/30 ,  G01R31/2837 ,  G01R31/2851 ,  G01R31/31727 ,  H03K3/0315

Abstract: A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source.

Abstract translation: 用于集成电路（IC）的劣化检测器，检测IC中的老化的方法和结合了劣化检测器的IC或方法。 在一个实施例中，劣化检测器包括：（1）耦合到功率门和时钟门的离线环形振荡器（RO），（2）耦合到时钟门的冷冻RO，（3）在线RO和（4） ）分析器，其耦合到离线RO，冷冻RO和在线RO，并且可操作以将劣化检测器置于正常状态，其中脱机RO与驱动电压源和时钟源两者断开，冷冻RO连接 到驱动电压源但与时钟源断开，并且在线RO连接到驱动电压源和时钟源。