公开(公告)号：US20200168767A1

公开(公告)日：2020-05-28

申请号：US16615835

申请日：2018-05-17

Applicant: Osram Opto Semiconductors GmbH

Inventor： Isabel OTTO ,  Anna KASPRZAK-ZABLOCKA ,  Christian LEIRER ,  Berthold HAHN

IPC: H01L33/38 ,  H01L31/0216 ,  H01L31/0224 ,  H01L33/40 ,  H01L33/00 ,  H01L33/32

Abstract: A semiconductor component may include a semiconductor body having a first semiconductor layer and a second semiconductor layer, a first main face and a second main face, opposite from the first main face, the first main face being formed by a surface of the first semiconductor layer and the second main face being formed by a surface of the second semiconductor layer. At least one side face may join the first main face to the second main face, an electrically conducting carrier layer, which covers the second main face at least in certain regions and extends from the second main face to at least one side face of the semiconductor body. An electrically conducting continuous deformation layer may cover the second main face at least in certain regions. The electrically conducting deformation layer may have an elasticity that is identical to or higher than the electrically conducting carrier layer.

公开(公告)号：US20180069147A1

公开(公告)日：2018-03-08

申请号：US15552259

申请日：2016-02-15

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Lutz HOEPPEL ,  Alexander F. PFEUFFER ,  Dominik SCHOLZ ,  Isabel OTTO ,  Norwin VON MALM ,  Stefan ILLEK

IPC: H01L33/00 ,  H01L21/02 ,  H01L33/48

CPC classification number: H01L33/0079 ,  H01L21/02 ,  H01L33/486 ,  H01L2221/67 ,  H01L2933/0033

Abstract: Disclosed is a method for producing a plurality of semiconductor chips (10). A composite (1), which comprises a carrier (4) and a semiconductor layer sequence (2, 3), is provided. Separating trenches (17) are formed in the semiconductor layer sequence (2, 3) along an isolation pattern (16). A filling layer (11) limiting the semiconductor layer sequence (2, 3) toward the separating trenches (17) is applied to a side of the semiconductor layer sequence (2, 3) facing away from the carrier (4). Furthermore, a metal layer (10) adjacent to the filling layer (11) is applied in the separating trenches (17). The semiconductor chips (20) are isolated by removing the metal layer (10) adjacent to the filling layer (11) in the separating trenches (17). Each isolated semiconductor chip (20) has one part of the semiconductor layer sequence (2, 3), and of the filling layer (11). Also disclosed is a semiconductor chip (10).

公开(公告)号：US20200152534A1

公开(公告)日：2020-05-14

申请号：US16615869

申请日：2018-05-17

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Christian LEIRER ,  Christian MUELLER ,  Isabel OTTO

IPC: H01L23/31 ,  H01L21/56

Abstract: A semiconductor component may have a semiconductor body, an electrically conductive carrier layer, and an electrically poorly conductive insulation. The semiconductor body may include a first semiconductor layer and a second semiconductor layer, a first main face and a second main face, situated opposite the first main face, wherein the first main face is formed by a surface of the first semiconductor layer and the second main face is formed by a surface of the second semiconductor layer. The electrically conductive carrier layer may regionally cover the second main face the carrier layer is structured in such a way that it has at least one contact-free depression. The insulation may be located between the carrier layer and the semiconductor body and covers at least part of the second main face and extends up to at least one lateral face of the semiconductor body.

公开(公告)号：US20180294378A1

公开(公告)日：2018-10-11

申请号：US16006765

申请日：2018-06-12

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Isabel OTTO ,  Alexander F. PFEUFFER ,  Dominik SCHOLZ

IPC: H01L33/08 ,  H01L27/15 ,  H01L33/38 ,  H01L21/3065 ,  H01L33/00 ,  H01L31/12 ,  H01L21/28 ,  H01L21/461 ,  H01L21/3213 ,  H01L21/311 ,  H01L25/16

CPC classification number: H01L33/08 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/461 ,  H01L25/167 ,  H01L27/156 ,  H01L31/12 ,  H01L33/00 ,  H01L33/38 ,  H01L2933/0016 ,  H01L2933/0033

Abstract: A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having—a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c),—an active layer (23), and—a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein—the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), B) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that—the first contact layer (41) and the second contact layer (42) are electrically separated from each other, and—the first contact layer (41) and the second contact layer (42) run parallel to each other.

公开(公告)号：US20170186911A1

公开(公告)日：2017-06-29

申请号：US15508899

申请日：2015-09-02

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Isabel OTTO ,  Alexander F. PFEUFFER ,  Dominik SCHOLZ

IPC: H01L33/08 ,  H01L33/38

CPC classification number: H01L33/08 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/461 ,  H01L25/167 ,  H01L27/156 ,  H01L31/12 ,  H01L33/00 ,  H01L33/38 ,  H01L2933/0016 ,  H01L2933/0033

Abstract: A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having —a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c), —an active layer (23), and —a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein —the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), B) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that —the first contact layer (41) and the second contact layer (42) are electrically separated from each other, and —the first contact layer (41) and the second contact layer (42) run parallel to each other.