公开(公告)号：US06627361B2

公开(公告)日：2003-09-30

申请号：US09901241

申请日：2001-07-09

申请人： Orest Bula ,  Michael S. Hibbs ,  Steven J. Holmes ,  Paul A. Rabidoux

发明人： Orest Bula ,  Michael S. Hibbs ,  Steven J. Holmes ,  Paul A. Rabidoux

IPC分类号： G03F900

CPC分类号： G03F1/36 ,  G03F7/095

摘要： An assist feature is formed on a lithographic reticle or mask using a hybrid resist and an exposure dose such that only an annular area is effectively exposed having a width that is potentially less than the minimum feature size that can be resolved by the mask exposure tool to simultaneously or sequentially form both a feature of interest and an assist feature for enhancing imaging of the feature of interest when the feature is printed to a wafer. Since the assist feature can be imaged simultaneously with the feature of interest or multiple assist features imaged concurrently, possibly between closely spaced features, data volume and mask writing time are greatly reduced. The invention is particularly applicable to the scaling of contact holes for connections to active devices in extremely high density integrated circuits.

摘要翻译： 使用混合抗蚀剂和曝光剂量在光刻掩模版或掩模上形成辅助特征，使得只有环形区域被有效地暴露，其宽度可能小于可由掩模曝光工具解析的最小特征尺寸， 同时或顺序地形成感兴趣的特征和当将特征印刷到晶片时增强感兴趣特征的成像的辅助特征。 由于可以与感兴趣的特征或同时成像的多个辅助特征（可能在紧密间隔的特征之间）同时成像辅助特征，所以数据量和掩模写入时间被大大减少。 本发明特别适用于用于连接到极高密度集成电路中的有源器件的接触孔的缩放。

公开(公告)号：US06531724B1

公开(公告)日：2003-03-11

申请号：US09686740

申请日：2000-10-10

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L29772

CPC分类号： H01L21/76897 ,  H01L21/76888 ,  H01L21/76895

摘要： A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.

摘要翻译： 一种用于在晶体管中形成栅极导体帽的方法，包括以下步骤：a）形成多晶硅栅极导体; b）掺杂多晶硅栅极; c）掺杂扩散区域; 以及d）通过从选择性氮化物沉积和选择性表面氮化中选择的氮化方法来封盖栅极导体。 所得到的晶体管可以包括封盖栅极导体和无边界扩散接触，其中通过选择性氮化物沉积和选择性表面氮化中选择的氮化方法发生封盖，并且其中在氮化方法期间掩模一部分栅极导体以留下开口 接触区域用于局部互连或门接触。

公开(公告)号：US06440801B1

公开(公告)日：2002-08-27

申请号：US09604901

申请日：2000-06-28

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Howard L. Kalter ,  Jack A. Mandelman ,  Paul A. Rabidoux ,  Jeffrey J. Welser

IPC分类号： H01L21336

CPC分类号： H01L27/11556 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10841 ,  H01L27/10897 ,  H01L27/115

摘要： A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are formed per pillar on opposite pillar sidewalls which are along the row direction. The threshold voltage of the pillar device is raised on the side of the pillar touching the passing wordline, thereby permanently shutting off the pillar device during the cell operation and isolating the pillar from the voltage variations on the passing wordline. The isolated wordlines allow individual cells to be addressed and written via direct tunneling, in both volatile and non-volatile memory cell configurations. For Gbit DRAM application, stack or trench capacitors may be formed on the pillars, or in trenches surrounding the pillars, respectively.

摘要翻译： 公开了一种具有支柱的紧密堆叠的垂直半导体器件阵列及其制造方法。 该阵列具有字线和位线列。 阵列具有垂直柱，每个具有两个字线，一个有效，另一个通过每个单元格。 在沿着行方向的相对的支柱侧壁上的每个柱形成两个字线。 支柱装置的阈值电压在柱体侧面升高，接触通过字线，从而在电池工作期间永久地关闭支柱装置，并将支柱与通过字线上的电压变化隔离。 孤立的字线允许在易失性和非易失性存储单元配置中通过直接隧道寻址和写入各个单元。 对于Gbit DRAM应用，可以在支柱上或在柱子周围的沟槽中分别形成堆叠或沟槽电容器。

公开(公告)号：US06440635B1

公开(公告)日：2002-08-27

申请号：US09675608

申请日：2000-09-29

申请人： Steven J. Holmes ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

发明人： Steven J. Holmes ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

IPC分类号： G03F7039

CPC分类号： G03F7/0045 ,  G03F7/095 ,  Y10S430/106 ,  Y10S430/11 ,  Y10S430/111

摘要： A photoresist having both positive and negative tone components resulting in a lower “k” factor than the single tone photoresist is disclosed. The hybrid resist may either have the negative tone resist or the positive tone resist as the major portion, while the other tone is a relatively minor portion. For examples, a positive tone resist may include a minor portion of a negative tone cross-linker or a negative tone resist may include positively acting functional groups. The hybrid resist of the present invention allows for wider exposure dosage windows, therefore increasing the yield or performance and line density.

摘要翻译： 公开了具有比单色光致抗蚀剂低的“k”因子的具有正和负色调分量的光致抗蚀剂。 混合抗蚀剂可以具有负色调抗蚀剂或正色调抗蚀剂作为主要部分，而另一种色调是相对较小的部分。 例如，正色调抗蚀剂可以包括负色调交联剂的较小部分或负色调抗蚀剂可以包括正性官能团。 本发明的混合抗蚀剂允许更宽的曝光剂量窗口，从而提高产量或性能和线密度。

公开(公告)号：US06221704B1

公开(公告)日：2001-04-24

申请号：US09089650

申请日：1998-06-03

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James S. Nakos ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  James S. Nakos ,  Paul A. Rabidoux

IPC分类号： H01L2144

CPC分类号： H01L21/76897 ,  H01L21/28123 ,  H01L21/823842 ,  H01L29/66575

摘要： Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a first conductive-forming layer on the first insulating layer; forming a second conductive layer on the first conductive-forming layer; forming a second insulating layer on the second conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the second conductive layer; depositing a third insulating material through the opening over the conductive layer; planarizing the second insulating layer and the third insulating material; removing the second insulating layer, the first conductive-forming layer and second conductive layer and the first insulating layer except beneath the third insulating material; and forming source/drain regions in the substrate.

公开(公告)号：US5945707A

公开(公告)日：1999-08-31

申请号：US56903

申请日：1998-04-07

申请人： Gary B. Bronner ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Jack A. Mandelman ,  Paul A. Rabidoux

发明人： Gary B. Bronner ,  Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Jack A. Mandelman ,  Paul A. Rabidoux

IPC分类号： H01L21/8242 ,  H01L29/72

CPC分类号： H01L27/10876 ,  H01L27/10861 ,  H01L27/10891

摘要： A memory cell having a grooved gate formed in a sub-lithographic groove, and methods of making thereof are disclosed. The groove extends the channel length to include the groove sidewalls and width of the groove. Sidewall sections of the channel located along the gate sidewalls have a larger length than the bottom channel section length located along the gate bottom width. Thus, the memory device is primarily controlled by the sidewall channel sections, instead of the bottom channel section. The groove may be a stepped groove formed by a two step etch to further increase the channel length and may be formed centered along the gate conductor width.

摘要翻译： 公开了一种在副光刻槽中形成有槽栅的存储单元及其制造方法。 凹槽延伸通道长度以包括凹槽侧壁和凹槽的宽度。 沿着栅极侧壁的通道的侧壁部分具有比沿着栅极底部宽度定位的底部通道部分长度更大的长度。 因此，存储器件主要由侧壁通道部分而不是底部通道部分控制。 沟槽可以是通过两步蚀刻形成的阶梯槽，以进一步增加沟道长度，并且可以沿着栅极导体宽度形成为中心。

公开(公告)号：US06372412B1

公开(公告)日：2002-04-16

申请号：US09021924

申请日：1998-02-10

申请人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

发明人： Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

IPC分类号： G03F730

CPC分类号： H01L28/82 ,  G03F7/0045 ,  G03F7/038 ,  G03F7/039 ,  G03F7/095 ,  H01L21/0274 ,  H01L21/3085

摘要： A photoresist composition is disclosed having both negative tone and positive tone responses, giving rise to spaces being formed in the areas of diffraction which are exposed to intermediate amounts of radiation energy. This resist material may be used to print doughnut shapes or may be subjected to a second masking step, to print lines. Additionally, larger and smaller features may be obtained using a gray-scale filter in the reticle, to create larger areas of intermediate exposure areas.

摘要翻译： 公开了具有负色调和正色调响应的光致抗蚀剂组合物，在曝光到中等辐射能量的衍射区域中形成空间。 该抗蚀剂材料可以用于印刷圆环形状或者可以进行第二掩蔽步骤以打印线。 另外，可以使用掩模版中的灰度滤光片获得更大和更小的特征，以产生更大面积的中间曝光区域。

公开(公告)号：US06284439B1

公开(公告)日：2001-09-04

申请号：US09107956

申请日：1998-06-30

申请人： Steven J. Holmes ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

发明人： Steven J. Holmes ,  Ahmad D. Katnani ,  Niranjan M. Patel ,  Paul A. Rabidoux

IPC分类号： G03F730

CPC分类号： G03F7/0045 ,  G03F7/095 ,  Y10S430/106 ,  Y10S430/11 ,  Y10S430/111

摘要： A photoresist having both positive and negative tone components resulting in a lower “k” factor than the single tone photoresist is disclosed. The hybrid resist may either have the negative tone resist or the positive tone resist as the major portion, while the other tone is a relatively minor portion. For examples, a positive tone resist may include a minor portion of a negative tone cross-linker or a negative tone resist may include positively acting functional groups. The hybrid resist of the present invention allows for wider exposure dosage windows, therefore increasing the yield or performance and line is density.

摘要翻译： 公开了具有比单色光致抗蚀剂低的“k”因子的具有正和负色调分量的光致抗蚀剂。 混合抗蚀剂可以具有负色调抗蚀剂或正色调抗蚀剂作为主要部分，而另一种色调是相对较小的部分。 例如，正色调抗蚀剂可以包括负色调交联剂的较小部分或负色调抗蚀剂可以包括正性官能团。 本发明的混合抗蚀剂允许更宽的曝光剂量窗口，因此增加产量或性能，线是密度。

公开(公告)号：US06200726B1

公开(公告)日：2001-03-13

申请号：US09170756

申请日：1998-10-13

申请人： Kuang-Jung Chen ,  Steven J. Holmes ,  Wu-Song Huang ,  Ahmad D. Katnani ,  Paul A. Rabidoux

发明人： Kuang-Jung Chen ,  Steven J. Holmes ,  Wu-Song Huang ,  Ahmad D. Katnani ,  Paul A. Rabidoux

IPC分类号： G03C173

CPC分类号： G03F7/038 ,  G03F7/0045 ,  G03F7/039 ,  G03F7/095 ,  H01L21/0274 ,  H01L21/3085 ,  H01L28/82 ,  Y10S430/106 ,  Y10S430/115 ,  Y10S430/128

摘要： A photo resist composition contains at least one photoacid generator (PAG), wherein at least two photoacids are produced upon exposure of the photo resist to actinic energy and wherein the photo resist is capable of producing a hybrid response. The function of providing generation of two photoacids in a hybrid resist is to optimize the use of hybrid resist by varying the hybrid space width. The at least two photoacids may differ in their effectiveness at catalyzing at least one mechanism of the hybrid response. In particular, one photoacid may be a weaker acid and another may be a stronger acid, wherein there exists a difference of at least four orders of magnitude between the acid dissociation constant (Ka) of the weaker acid and the stronger acid. A method for optimizing space width in a hybrid photo resist includes the steps of: 1) selecting a desired space width; 2) selecting at least one photoacid generator (PAG), wherein at least two photoacids will be produced upon exposure to actinic energy in relative proportions sufficient to produce the desired space width in the hybrid photo resist; and 3) forming a hybrid photo resist composition comprising the at least one PAG. The step of selecting at least one PAG may include first determining the space width produced alone by each photoacid in a group of candidate photoacids and then selecting the photoacids and corresponding at least one PAG that will produce the desired space width.

摘要翻译： 光致抗蚀剂组合物含有至少一种光致酸发生剂（PAG），其中当光致抗蚀剂暴露于光化能时，产生至少两种光酸，并且其中光致抗蚀剂能产生杂化响应。 在混合抗蚀剂中提供两种光酸的产生的功能是通过改变混合空间宽度来优化混合抗蚀剂的使用。 至少两种光酸在催化至少一种混合反应机制方面的有效性可能不同。 特别地，一种光致酸可以是较弱的酸，而另一种可能是较强的酸，其中在较弱酸的酸解离常数（Ka）和较强酸之间存在至少四个数量级的差异。 一种用于优化混合光刻胶中的空间宽度的方法包括以下步骤：1）选择期望的空间宽度; 2）选择至少一种光致酸产生剂（PAG），其中当以相对比例暴露于足以产生混合光致抗蚀剂中所需空间宽度的光化能时，将产生至少两种光酸; 和3）形成包含所述至少一种PAG的混合光刻胶组合物。 选择至少一个PAG的步骤可以包括首先确定由一组候选光酸中的每个光酸酸单独产生的空间宽度，然后选择将产生所需空间宽度的光酸和相应的至少一个PAG。

公开(公告)号：US6150256A

公开(公告)日：2000-11-21

申请号：US183338

申请日：1998-10-30

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Paul A. Rabidoux

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76825 ,  H01L21/0274 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76811

摘要： The present invention provides for an improved method of creating vias and trenches during microchip fabrication. According to the invention, the vias and trenches are self-aligned during the photolithography process by using two layers of specially selected resists and exposing the resists such that the lower resist is exposed only where an opening has been formed in the upper resist layer. This self-aligning enables the vias to be printed as elongated shapes, which allows for the use of particularly effective image enhancement techniques. The invention further provides a simplified procedure for creating vias and trenches, in that only one etch step is required to simultaneously create both vias and trenches. An alternative embodiment of the invention allows looped or linked images, such as those printed using image enhancement techniques, to be trimmed to form isolated features.

摘要翻译： 本发明提供了一种在微芯片制造期间产生通孔和沟槽的改进方法。 根据本发明，通过使用两层特别选择的抗蚀剂，在光刻工艺期间，通孔和沟槽是自对准的，并且使抗蚀剂曝光，使得下抗蚀剂仅在上抗蚀剂层中形成开口的地方露出。 这种自对准使通孔能够被印制成细长的形状，这允许使用特别有效的图像增强技术。 本发明还提供了一种用于产生通孔和沟槽的简化过程，因为仅需要一个蚀刻步骤来同时产生通孔和沟槽。 本发明的替代实施例允许将被修剪以形成隔离特征的循环或链接的图像，诸如使用图像增强技术印刷的图像。