公开(公告)号：US09130564B2

公开(公告)日：2015-09-08

申请号：US13850251

申请日：2013-03-25

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： Christopher N. Brindle ,  Michael A. Stuber ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George Imthurn ,  Robert B. Welstand ,  Mark L. Burgener

IPC分类号： H01L29/66 ,  H03K17/16 ,  H01L29/786

CPC分类号： H03K17/162 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/78609 ,  H01L29/78615 ,  H01L29/78681 ,  H01L29/78684 ,  H03K17/687 ,  H03K2217/0018

摘要： A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

摘要翻译： 公开了一种用于改善使用累积电荷吸收（ACS）的MOSFET器件的线性特性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个示例性实施例中，具有至少一个SOI MOSFET的电路被配置为在累积电荷状态下操作。 当FET在累积电荷状态下工作时，可操作地耦合到SOI MOSFET的主体的累积电荷宿消除，去除或以其他方式控制累积电荷，从而降低寄生偏离态源极至漏极间电容的非线性 的SOI MOSFET。 在利用改进的SOI MOSFET器件实现的RF开关电路中，当SOI MOSFET在累积电荷状态下工作时，通过去除或以其他方式控制累积电荷来减小谐波和互调失真。

公开(公告)号：US20140151704A1

公开(公告)日：2014-06-05

申请号：US13831067

申请日：2013-03-14

申请人： Peregrine Semiconductor Corporation

发明人： Hiroshi Domyo ,  Michael McCafferty ,  Alain Duvallet ,  Masaki Sato ,  Christopher O'Brien ,  Anthony Mark Miscione ,  George Imthurn

IPC分类号： H01L21/322 ,  H01L29/36

CPC分类号： H01L21/3226 ,  H01L21/02052 ,  H01L21/3221 ,  H01L21/76251 ,  H01L21/76256 ,  H01L23/26 ,  H01L23/3128 ,  H01L29/36 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals or a sacrificial layer to limit or remove substrate contaminants and reduce substrate surface damage. Other embodiments may be described and claimed.

摘要翻译： 本文描述了制备用于随后与半导体层接合的衬底的实施例。 可以用一种或多种化学品或牺牲层制备基底以限制或去除基底污染物并减少基底表面损伤。 可以描述和要求保护其他实施例。

公开(公告)号：US09390942B2

公开(公告)日：2016-07-12

申请号：US13831067

申请日：2013-03-14

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： Hiroshi Domyo ,  Michael McCafferty ,  Alain Duvallet ,  Masaki Sato ,  Christopher O'Brien ,  Anthony Mark Miscione ,  George Imthurn

IPC分类号： H01L21/332 ,  H01L21/322 ,  H01L21/02 ,  H01L29/36 ,  H01L23/31 ,  H01L21/762 ,  H01L23/26

CPC分类号： H01L21/3226 ,  H01L21/02052 ,  H01L21/3221 ,  H01L21/76251 ,  H01L21/76256 ,  H01L23/26 ,  H01L23/3128 ,  H01L29/36 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of preparing substrates for subsequent bonding with semiconductor layer are described herein. A substrate may be prepared with one or more chemicals or a sacrificial layer to limit or remove substrate contaminants and reduce substrate surface damage. Other embodiments may be described and claimed.

摘要翻译： 本文描述了制备用于随后与半导体层接合的衬底的实施例。 可以用一种或多种化学品或牺牲层制备基底以限制或去除基底污染物并减少基底表面损伤。 可以描述和要求保护其他实施例。

公开(公告)号：US20160191040A1

公开(公告)日：2016-06-30

申请号：US14845154

申请日：2015-09-03

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： Christopher N. Brindle ,  Michael A. Stuber ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George Imthurn ,  Robert B. Welstand ,  Mark L. Burgener

IPC分类号： H03K17/16 ,  H03K17/687 ,  H01L29/06 ,  H01L29/786 ,  H01L29/10

CPC分类号： H03K17/162 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/78609 ,  H01L29/78615 ,  H01L29/78681 ,  H01L29/78684 ,  H03K17/687 ,  H03K2217/0018

摘要： A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

公开(公告)号：US09780775B2

公开(公告)日：2017-10-03

申请号：US14845154

申请日：2015-09-03

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： Christopher N. Brindle ,  Michael A. Stuber ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George Imthurn ,  Mark L. Burgener

IPC分类号： H01L29/66 ,  H03K17/16 ,  H01L29/786 ,  H01L29/06 ,  H01L29/10 ,  H03K17/687

CPC分类号： H03K17/162 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/78609 ,  H01L29/78615 ,  H01L29/78681 ,  H01L29/78684 ,  H03K17/687 ,  H03K2217/0018

摘要： A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

公开(公告)号：US20130293280A1

公开(公告)日：2013-11-07

申请号：US13850251

申请日：2013-03-25

申请人： PEREGRINE SEMICONDUCTOR CORPORATION

发明人： Christopher N. Brindle ,  Michael A. Stuber ,  Dylan J. Kelly ,  Clint L. Kemerling ,  George Imthurn ,  Robert B. Welstand ,  Mark L. Burgener

IPC分类号： H03K17/16

CPC分类号： H03K17/162 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/78609 ,  H01L29/78615 ,  H01L29/78681 ,  H01L29/78684 ,  H03K17/687 ,  H03K2217/0018

摘要： A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

摘要翻译： 公开了一种用于改善使用累积电荷吸收（ACS）的MOSFET器件的线性特性的方法和装置。 该方法和装置适于去除，减少或以其他方式控制SOI MOSFET中的累积电荷，从而产生FET性能特性的改进。 在一个示例性实施例中，具有至少一个SOI MOSFET的电路被配置为在累积电荷状态下操作。 当FET在累积电荷状态下工作时，可操作地耦合到SOI MOSFET的主体的累积电荷吸收器消除，去除或以其他方式控制累积电荷，从而降低寄生偏离态源极至漏极间电容的非线性 的SOI MOSFET。 在利用改进的SOI MOSFET器件实现的RF开关电路中，当SOI MOSFET在累积电荷状态下工作时，通过去除或以其他方式控制累积电荷来减小谐波和互调失真。