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公开(公告)号：US07342518B2
公开(公告)日：2008-03-11
申请号：US10761158
申请日：2004-01-20
IPC分类号： H03M7/00
CPC分类号： H04L7/0029 , G11B2020/10675 , H03H17/028 , H03H17/0628 , H04L7/005
摘要： A method and apparatus of converting a data signal in a digital rate converter including upsampling the input data signal at an input sampling rate to an intermediate data signal at an intermediate sampling rate, where the intermediate data signal sample values are stored in a buffer. A plurality of buffer position values are provided from a subset of buffer positions of the buffer to an interpolator, the subset of buffer positions being dependent upon a position indicator. An output data signal is provided by the interpolator at an output sampling rate, where the value of the output data signal is dependent upon a fractional indicator provided to the interpolator. The input sampling rate is based on a first clock signal and the output sampling rate is based on a second clock signal, wherein the first and second clock signal are independent of each other.
摘要翻译： 一种在数字速率转换器中转换数据信号的方法和装置，包括以输入采样率将输入数据信号上采样到中间数据信号，其中中间数据信号采样值存储在缓冲器中。 从缓冲器的缓冲器位置的子集到内插器提供多个缓冲器位置值，缓冲器位置的子集取决于位置指示器。 输出数据信号由插值器以输出采样率提供，其中输出数据信号的值取决于提供给内插器的分数指示符。 输入采样率基于第一时钟信号，并且输出采样率基于第二时钟信号，其中第一和第二时钟信号彼此独立。
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2.发明授权Digital saturation handling in integral noise shaping of pulse width modulation 有权数字饱和处理在脉冲宽度调制的积分噪声整形中公开(公告)号：US07227487B1
公开(公告)日：2007-06-05
申请号：US11273286
申请日：2005-11-14
IPC分类号： H03M1/82
摘要： An audio amplifier includes a digital signal processor (DSP) that contains a noise shaping quantizer having an integrating error amplifier. The integrating error amplifier contains integrators connected in a feedback loop, a summer supplied with an output of each of the integrators, and a saturation function module producing a saturation function. A multiplier is disposed between each pair of adjacent integrators. The multiplier receives a signal from one of the adjacent integrators and the saturation function and supplies a signal to the other of the adjacent integrators. The saturation function decreases the effect of all of the integrators except an integrator to which an input signal to the integrating amplifier is supplied using an input signal to and/or an output signal from the noise shaping quantizer. This permits the duty ratio of the output signal from the noise shaping quantizer to extend from 0% to 100%.
摘要翻译： 音频放大器包括包含具有积分误差放大器的噪声整形量化器的数字信号处理器（DSP）。 积分误差放大器包含连接在反馈回路中的积分器，与每个积分器的输出相加的夏季以及产生饱和功能的饱和功能模块。 在每对相邻的积分器之间设置乘法器。 乘法器接收来自相邻积分器之一的信号和饱和度函数，并向相邻的积分器中的另一个提供信号。 饱和功能降低了除了积分器之外的所有积分器的影响，使用来自噪声整形量化器的输入信号和/或来自噪声整形量化器的输出信号向积分放大器提供输入信号。 这允许来自噪声整形量化器的输出信号的占空比从0％延伸到100％。
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3.发明申请NOISE POWER THRESHOLDING AND BALANCING FOR LONG TERM EVOLUTION (LTE) SYMBOL DETECTION 有权用于长时间演进（LTE）符号检测的噪声功率平衡和平衡公开(公告)号：US20140064350A1
公开(公告)日：2014-03-06
申请号：US13597738
申请日：2012-08-29
CPC分类号： H04B7/0854 , H04B7/0857 , H04L5/0023 , H04L25/03178 , H04L25/03254 , H04L25/03292
摘要： A noise thresholder of a baseband modem integrated circuit (BMIC) compares measured noise variances on corresponding receiver paths to a pre-established threshold minimum value. The noise thresholder assigns as a noise variance value for a corresponding receiver path either (a) a measured noise variance value for each receiver path having a measured noise variance that is larger than the pre-established threshold minimum, and (b) the pre-established threshold minimum value for each receiver path having a measured noise variance that is less than or equal to the pre-established threshold minimum value. A noise balancer performs noise balancing to provide a same signal to noise ratio (SNR) across all receiver paths, based on the assigned noise variances provided at the noise thresholder. A detection engine utilizes a lowest assigned noise variance value and outputs yielded by the noise balancer to simplify equalization computations while providing a high performance symbol detection capability.
摘要翻译： 基带调制解调器集成电路（BMIC）的噪声阈值器将相应接收器路径上的测量的噪声方差与预先建立的阈值最小值进行比较。 噪声阈值分配器作为相应接收机路径的噪声方差值，分配（a）每个具有大于预先设定的阈值最小值的噪声方差的接收机路径的测量噪声方差值，以及（b） 具有小于或等于预先建立的阈值最小值的测量噪声方差的每个接收器路径的建立阈值最小值。 噪声平衡器基于在噪声阈值器处提供的分配的噪声方差来执行噪声平衡以在所有接收机路径上提供相同的信噪比（SNR）。 检测引擎利用噪声平衡器产生的最低分配噪声方差值和输出，以简化均衡计算，同时提供高性能符号检测能力。
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公开(公告)号：US5165038A
公开(公告)日：1992-11-17
申请号：US536198
申请日：1990-06-11
申请人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
发明人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
IPC分类号： G06F15/16 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/167 , G06F15/17 , G06F15/173 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Global registers for a multiprocessor system support multiple parallel access paths for simultaneous operations on separate sets of global registers, each set of global registers referred to as a global register file. An arbitration mechanism associated with the global registers is used for resolving multiple, simultaneous requests to a single global register file. An arithmetic and logical unit (ALU) is also associated with each global register file for allowing atomic arithmetic operations to be performed on the entire register value for any of the global registers in that global register file.
摘要翻译： 用于多处理器系统的全局寄存器支持多个并行访问路径，用于在单独的全局寄存器集合上同时操作，每组全局寄存器被称为全局寄存器文件。 与全局寄存器相关联的仲裁机制用于解析对单个全局寄存器文件的多个同时请求。 算术和逻辑单元（ALU）也与每个全局寄存器文件相关联，以允许对该全局寄存器文件中的任何全局寄存器的整个寄存器值执行原子算术运算。
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5.发明授权Noise power thresholding and balancing for long term evolution (LTE) symbol detection 有权用于长期演进（LTE）符号检测的噪声功率阈值和平衡公开(公告)号：US08724754B2
公开(公告)日：2014-05-13
申请号：US13597738
申请日：2012-08-29
IPC分类号： H04B7/10
CPC分类号： H04B7/0854 , H04B7/0857 , H04L5/0023 , H04L25/03178 , H04L25/03254 , H04L25/03292
摘要： A noise thresholder of a baseband modem integrated circuit (BMIC) compares measured noise variances on corresponding receiver paths to a pre-established threshold minimum value. The noise thresholder assigns as a noise variance value for a corresponding receiver path either (a) a measured noise variance value for each receiver path having a measured noise variance that is larger than the pre-established threshold minimum, and (b) the pre-established threshold minimum value for each receiver path having a measured noise variance that is less than or equal to the pre-established threshold minimum value. A noise balancer performs noise balancing to provide a same signal to noise ratio (SNR) across all receiver paths, based on the assigned noise variances provided at the noise thresholder. A detection engine utilizes a lowest assigned noise variance value and outputs yielded by the noise balancer to simplify equalization computations while providing a high performance symbol detection capability.
摘要翻译： 基带调制解调器集成电路（BMIC）的噪声阈值器将相应接收器路径上的测量的噪声方差与预先建立的阈值最小值进行比较。 噪声阈值分配器作为相应接收机路径的噪声方差值，分配（a）每个具有大于预先设定的阈值最小值的噪声方差的接收机路径的测量噪声方差值，以及（b） 具有小于或等于预先建立的阈值最小值的测量噪声方差的每个接收器路径的建立阈值最小值。 噪声平衡器基于在噪声阈值器处提供的分配的噪声方差来执行噪声平衡以在所有接收机路径上提供相同的信噪比（SNR）。 检测引擎利用噪声平衡器产生的最低分配噪声方差值和输出，以简化均衡计算，同时提供高性能符号检测能力。
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6.发明授权Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers 失效用于在处理器被分配处理ID号的多处理器系统中并行处理处理器的快速中断机制
公开(公告)号：US5193187A
公开(公告)日：1993-03-09
申请号：US898387
申请日：1992-06-10
申请人： Robert E. Strout, II , George A. Spix , Edward C. Miller , Anthony R. Schooler , Alexander A. Silbey , Andrew E. Phelps , Brian D. Vanderwarn , Gregory G. Gaertner
发明人： Robert E. Strout, II , George A. Spix , Edward C. Miller , Anthony R. Schooler , Alexander A. Silbey , Andrew E. Phelps , Brian D. Vanderwarn , Gregory G. Gaertner
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/07 , G06F11/36 , G06F13/24 , G06F15/173 , G06F15/78 , G06F15/80
CPC分类号： G06F11/0724 , G06F11/0712 , G06F11/0793 , G06F11/362 , G06F13/24 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F11/36
摘要： A fast interrupt mechanism is capable of simultaneously interrupting a community of associated processors in a multiprocessor system. The fast interrupt mechanism enables the more effective debugging of software executing on a multiprocessor system by allowing all of the processors in a community associated with a parallel process to be halted within a limited number of clock cycles following a hardware exception or processor breakpoint. The fast interrupt mechanism consists of a set of registers that are used to identify associations among multiple processors, a comparison matrix that is used to select processors to be interrupted, a network of interconnections that transmit interrupt events to and from the processors, and elements in the processors that create and respond to fast interrupt events.
摘要翻译： 快速中断机制能够同时中断多处理器系统中相关处理器的社区。 快速中断机制使得能够在多处理器系统上执行软件的更有效的调试，允许与并行进程相关联的社区中的所有处理器在硬件异常或处理器断点之后的有限数量的时钟周期内停止。 快速中断机制包括一组用于识别多个处理器之间的关联的寄存器，用于选择要中断的处理器的比较矩阵，向处理器发送中断事件的互连网络，以及从处理器传送中断事件的互连网络 处理器创建并响应快速中断事件。
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公开(公告)号：US06463110B1
公开(公告)日：2002-10-08
申请号：US09813708
申请日：2001-03-21
IPC分类号： H04L700
CPC分类号： H04L7/0029 , H03H17/0286 , H03H17/0294 , H03H17/06 , H03H2017/0245 , H03H2218/12
摘要： A method for performing timing synchronization between digital input data and a system clock in a communication device includes providing a system clock rate that is higher than a data clock rate and sampling the input data at intervals in the system clock periods within the data clock period. The method includes adjusting the timing between the digital input data and the system clock by either shortening the number of system clock periods and sampling intervals, or lengthening the number of system clock periods and sampling the input data at normal intervals and providing data insertion to fill one of the extra system clock periods, such that more data samples are provided in the data clock period.
摘要翻译： 一种用于在通信设备中的数字输入数据和系统时钟之间执行定时同步的方法包括：提供高于数据时钟速率的系统时钟速率，并且在数据时钟周期内的系统时钟周期内以间隔采样输入数据。 该方法包括通过缩短系统时钟周期和采样间隔的数量来调整数字输入数据和系统时钟之间的定时，或延长系统时钟周期数，并以正常间隔对输入数据进行采样，并提供数据插入以填充 一个额外的系统时钟周期，使得在数据时钟周期中提供更多的数据样本。
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8.发明授权公开(公告)号：US07916811B2
公开(公告)日：2011-03-29
申请号：US10776982
申请日：2004-02-11
IPC分类号： H04L27/14
摘要： A method for improving burst acquisition in a receiver includes receiving a signal, and performing a sync word search on the signal, wherein the sync word search includes performing a hybrid synchronization technique, the hybrid synchronization technique including both a lower order modulation (e.g., BPSK) detection and correlation process and a higher order modulation (e.g., QPSK) detection and correlation process.
摘要翻译： 一种用于改善接收机中的脉冲串采集的方法，包括：接收信号，对信号执行同步字搜索，其中同步字搜索包括执行混合同步技术，混合同步技术包括低阶调制（例如，BPSK ）检测和相关过程和更高阶调制（例如，QPSK）检测和相关过程。
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公开(公告)号：US06788731B2
公开(公告)日：2004-09-07
申请号：US10133149
申请日：2002-04-26
申请人： Yun Kim , David P. Gurney , Anthony R. Schooler , Zhuan Ye
发明人： Yun Kim , David P. Gurney , Anthony R. Schooler , Zhuan Ye
IPC分类号： H04L2730
CPC分类号： G06F17/15 , H04B1/707 , H04B1/7095 , H04B2201/709727
摘要： A programmable correlator for a communication system includes an input queue coupled with an analog-to-digital converter (ADC). The input queue includes a random access memory (RAM) wherein sampled data streams from the ADC are written into the RAM. The input queue has two banks of memory of width 2M. A flexible complex correlator is operable on M samples. The correlator is coupled to read M complex samples out of 2M samples from the input queue. A pseudo-noise (PN) crossbar unit operates to rotate a generated PN code to match a rotation of the input queue data in the complex correlator.
摘要翻译： 用于通信系统的可编程相关器包括与模数转换器（ADC）耦合的输入队列。 输入队列包括随机存取存储器（RAM），其中来自ADC的采样数据流被写入RAM。 输入队列具有宽度为2M的两组存储器。 灵活的复相关器可在M个样本上操作。 相关器被耦合以从输入队列中读取2M个样本中的M个复杂样本。 伪噪声（PN）交叉单元操作以旋转所产生的PN码以匹配复相关器中的输入队列数据的旋转。
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10.发明授权Method and apparatus for accessing global registers in a multiprocessor system 失效用于在多处理器系统中访问全局寄存器的方法和装置
公开(公告)号：US5524255A
公开(公告)日：1996-06-04
申请号：US379123
申请日：1995-01-27
申请人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
发明人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/17 , G06F15/173 , G06F15/78 , G06F15/80 , G06F15/163
CPC分类号： G06F9/3004 , G06F15/17 , G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30043 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A global register system provides communication and coordination among a plurality of processors sharing a common memory in a multiprocessor system which access one or more registers within a shared resource circuit that is separate from the common memory and is symmetrically accessible by the plurality of processors in the multiprocessor system. The global register system is accessed by direct addresses determined by the processor from a previously assigned indirect address and an instruction accessing the data stored in global registers. Arithmetic or logic operation on a data value stored in a selected one of the registers are performed by the global register system independent from the processors or the common memory in order to modify the data value in the selected global register as part of an atomic operation performed in response to a single read-and-modify instruction received from one of the processors.
摘要翻译： 全局注册系统提供在多处理器系统中共享公共存储器的多个处理器之间的通信和协调，多处理器系统访问共享资源电路内的一个或多个与公共存储器分离的寄存器，并且可由多个处理器对称地访问 多处理器系统 全局寄存器系统由处理器从先前分配的间接地址确定的直接地址和访问存储在全局寄存器中的数据的指令访问。 存储在所选择的一个寄存器中的数据值的算术或逻辑运算由独立于处理器或公共存储器的全局寄存器系统执行，以便修改所选择的全局寄存器中的数据值，作为执行的原子操作的一部分 响应于从一个处理器接收的单个读取和修改指令。
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