公开(公告)号：US20150115423A1

公开(公告)日：2015-04-30

申请号：US14401556

申请日：2013-05-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Kenya Yamashita

IPC: H01L23/34 ,  H01L23/28 ,  H01L27/06 ,  H01L23/495

CPC classification number: H01L23/49548 ,  H01L23/043 ,  H01L23/24 ,  H01L23/28 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/07 ,  H01L25/18 ,  H01L27/0629 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/84

Abstract: Included are: the third frame which is electrically connected to the first intermediate frame and is arranged above the first frame; the fourth frame which is electrically connected to the second intermediate frame and is arranged above the second frame; the electric source terminal part which is provided on an extension of the first frame; the ground terminal part which is provided on an extension of the fourth frame; and the output terminal part which is provided on an extension to which the second frame and the third frame are electrically joined, wherein the third frame and the fourth frame are arranged in parallel with each other, and the electric source terminal part, the ground terminal part and the output terminal part are arranged in a manner such that induced electric voltages, which are generated in the third frame and the fourth frame, become in reverse directions with each other.

Abstract translation: 包括：电连接到第一中间框架并且布置在第一框架上方的第三框架; 所述第四框架电连接到所述第二中间框架并且布置在所述第二框架的上方; 所述电源端子部设置在所述第一框架的延伸部上; 所述接地端子部分设置在所述第四框架的延伸部上; 以及设置在第二框架和第三框架电连接的延伸部上的输出端子部分，其中第三框架和第四框架彼此平行地布置，并且电源端子部分，接地端子 部分和输出端子部分的布置方式使得在第三帧和第四帧中产生的感应电压彼此相反。

公开(公告)号：US09520344B2

公开(公告)日：2016-12-13

申请号：US14401556

申请日：2013-05-07

Applicant: Panasonic Intellectual Property Management Co., Ltd

Inventor： Kenya Yamashita

IPC: H01L23/24 ,  H01L23/28 ,  H01L23/495 ,  H01L23/34 ,  H01L23/043 ,  H01L25/07 ,  H01L25/18 ,  H01L27/06 ,  H01L23/00 ,  H01L23/373 ,  H01L23/433 ,  H01L23/498

CPC classification number: H01L23/49548 ,  H01L23/043 ,  H01L23/24 ,  H01L23/28 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49589 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/07 ,  H01L25/18 ,  H01L27/0629 ,  H01L2224/32245 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40247 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01005 ,  H01L2224/84

Abstract: Included are: the third frame which is electrically connected to the first intermediate frame and is arranged above the first frame; the fourth frame which is electrically connected to the second intermediate frame and is arranged above the second frame; the electric source terminal part which is provided on an extension of the first frame; the ground terminal part which is provided on an extension of the fourth frame; and the output terminal part which is provided on an extension to which the second frame and the third frame are electrically joined, wherein the third frame and the fourth frame are arranged in parallel with each other, and the electric source terminal part, the ground terminal part and the output terminal part are arranged in a manner such that induced electric voltages, which are generated in the third frame and the fourth frame, become in reverse directions with each other.

Abstract translation: 包括：电连接到第一中间框架并且布置在第一框架上方的第三框架; 所述第四框架电连接到所述第二中间框架并且布置在所述第二框架的上方; 所述电源端子部设置在所述第一框架的延伸部上; 所述接地端子部分设置在所述第四框架的延伸部上; 以及设置在第二框架和第三框架电连接的延伸部上的输出端子部分，其中第三框架和第四框架彼此平行地布置，并且电源端子部分，接地端子 部分和输出端子部分的布置方式使得在第三帧和第四帧中产生的感应电压彼此相反。

公开(公告)号：US10763395B2

公开(公告)日：2020-09-01

申请号：US16295115

申请日：2019-03-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hiroshi Ohno ,  Kenya Yamashita

IPC: H01L33/22 ,  H01L33/00 ,  H01L33/32

Abstract: A flip-chip light emitting diode element capable of reducing lateral resistance. The flip-chip light emitting diode element includes a stacked body structure configured by sequentially stacking a first n-type group III nitride semiconductor layer having a carrier concentration that is at least 1×1019 cm−3 but less than 3×1020 cm−3, a second n-type group III nitride semiconductor layer having a carrier concentration that is at least 5×1017 cm−3 but less than 1×1019 cm−3, a light-emitting layer formed by a group III nitride semiconductor, and a p-type group III nitride semiconductor layer. A height of unevenness on an interface between the first n-type group III nitride semiconductor layer and the second n-type group III nitride semiconductor layer is greater than that of unevenness of an interface between the second n-type group III nitride semiconductor layer and the light emitting layer.

公开(公告)号：US10923346B2

公开(公告)日：2021-02-16

申请号：US16562684

申请日：2019-09-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Akihiko Ishibashi ,  Hiroshi Ono ,  Kenya Yamashita

IPC: H01L21/02 ,  C30B29/22 ,  H01L29/20 ,  H01L21/3063 ,  C30B25/18

Abstract: A Group III nitride semiconductor for growing a high-quality crystal having a low defect density and a method for producing the Group III nitride semiconductor. The Group III nitride semiconductor includes an RAMO4 substrate including a single crystal represented by the general formula RAMO4 (where R represents one or more trivalent elements selected from the group consisting of Sc, In, Y and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn and Cd); a p-type Group III nitride crystal layer disposed on the RAMO4 substrate; a plurality of n-type Group III nitride crystal layers disposed on the p-type Group III nitride crystal layer; and a Group III nitride crystal layer disposed on the n-type Group III nitride crystal layers.