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1.发明申请MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM 有权使用堆叠存储器设备的存储器系统和方法，以及使用存储器系统的系统公开(公告)号：US20110296227A1
公开(公告)日：2011-12-01
申请号：US13209273
申请日：2011-08-12
IPC分类号： G06F1/08
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
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2.发明授权Memory system and method using stacked memory device dice, and system using the memory system 有权内存系统和方法采用堆叠式存储设备骰子，系统采用内存系统公开(公告)号：US08010866B2
公开(公告)日：2011-08-30
申请号：US12961291
申请日：2010-12-06
IPC分类号： H03M13/00
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其它信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
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3.发明授权Memory system and method using stacked memory device dice, and system using the memory system 有权内存系统和方法采用堆叠式存储设备骰子，系统采用内存系统公开(公告)号：US07855931B2
公开(公告)日：2010-12-21
申请号：US12176951
申请日：2008-07-21
IPC分类号： G11C8/00
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
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4.发明授权Memory system and method using stacked memory device dice, and system using the memory system 有权内存系统和方法采用堆叠式存储设备骰子，系统采用内存系统公开(公告)号：US08533416B2
公开(公告)日：2013-09-10
申请号：US13209273
申请日：2011-08-12
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
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5.发明申请METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES 有权修复高容量/高带宽存储器件的方法和装置公开(公告)号：US20100005376A1
公开(公告)日：2010-01-07
申请号：US12166814
申请日：2008-07-02
CPC分类号： G06F11/1092 , G06F11/08 , G06F11/1048 , G11C29/808 , H03M13/09
摘要： Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.
摘要翻译： 公开了可以包括通过硅通孔彼此连接的多个堆叠的存储器件管芯和逻辑管芯的存储器系统，系统和方法。 一个这样的逻辑管芯包括产生与写入数据相对应的错误检查代码的错误代码生成器。 错误检查码存储在存储器件芯片中，随后与随后从存储器件芯片读取的数据产生的错误校验码进行比较。 在代码不匹配的情况下，可以产生错误信号。 逻辑管芯可能包含一个控制器，用于记录从中读取数据的地址。 控制器或存储器访问设备可以将访问重定向到记录地址处的存储设备裸片。 控制器还可以检查产生误差信号的地址或数据，以识别通孔硅通孔中的故障。
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6.发明授权Method and apparatus for repairing high capacity/high bandwidth memory devices 有权用于修复高容量/高带宽存储器件的方法和装置公开(公告)号：US08756486B2
公开(公告)日：2014-06-17
申请号：US12166814
申请日：2008-07-02
CPC分类号： G06F11/1092 , G06F11/08 , G06F11/1048 , G11C29/808 , H03M13/09
摘要： Memory systems, systems and methods are described that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.
摘要翻译： 描述了可以包括通过硅通孔彼此连接的多个堆叠的存储器件管芯和逻辑管芯的存储器系统，系统和方法。 一个这样的逻辑管芯包括产生与写入数据相对应的错误检查代码的错误代码生成器。 错误检查码存储在存储器件芯片中，随后与随后从存储器件芯片读取的数据产生的错误校验码进行比较。 在代码不匹配的情况下，可以产生错误信号。 逻辑管芯可能包含一个控制器，用于记录从中读取数据的地址。 控制器或存储器访问设备可以将访问重定向到记录地址处的存储设备裸片。 控制器还可以检查产生误差信号的地址或数据，以识别通孔硅通孔中的故障。
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7.发明申请MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING READ DATA 有权用于控制接收读取数据的时序的存储器系统和方法公开(公告)号：US20090300314A1
公开(公告)日：2009-12-03
申请号：US12128883
申请日：2008-05-29
申请人： Paul A. LaBerge , James B. Johnson
发明人： Paul A. LaBerge , James B. Johnson
IPC分类号： G06F12/00
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0611 , G06F3/0629 , G06F3/0673 , G06F3/0689 , G06F5/06 , G06F13/1689 , G06F2003/0697 , G11C7/1051 , G11C7/222 , Y02D10/14
摘要： Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.
摘要翻译： 本发明的实施例提供了具有共享用于传输读取数据的接口的多个存储器件的存储器系统。 控制器可以识别发送到不同存储器件的连续读取请求。 为了避免接口上的数据争用，例如，控制器可被配置为延迟时间，直到对应于第二读请求的读取数据被放置在接口上。
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8.发明授权Memory systems and methods for controlling the timing of receiving read data 有权用于控制接收读取数据的定时的存储器系统和方法公开(公告)号：US08521979B2
公开(公告)日：2013-08-27
申请号：US12128883
申请日：2008-05-29
申请人： Paul A. LaBerge , James B. Johnson
发明人： Paul A. LaBerge , James B. Johnson
CPC分类号： G06F3/0659 , G06F3/0604 , G06F3/0611 , G06F3/0629 , G06F3/0673 , G06F3/0689 , G06F5/06 , G06F13/1689 , G06F2003/0697 , G11C7/1051 , G11C7/222 , Y02D10/14
摘要： Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface.
摘要翻译： 本发明的实施例提供了具有共享用于传输读取数据的接口的多个存储器件的存储器系统。 控制器可以识别发送到不同存储器件的连续读取请求。 为了避免接口上的数据争用，例如，控制器可被配置为延迟时间，直到对应于第二读请求的读取数据被放置在接口上。
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公开(公告)号：US20120213012A1
公开(公告)日：2012-08-23
申请号：US13460245
申请日：2012-04-30
申请人： James Brian Johnson , Paul A. LaBerge , Jake Klier
发明人： James Brian Johnson , Paul A. LaBerge , Jake Klier
CPC分类号： G11C7/1078 , G11C5/00 , G11C7/1051 , G11C7/1066 , G11C7/1093
摘要： A strobe signal is received in a device and execution of an operation in the device is delayed when the strobe signal includes a preamble. Additional apparatus, systems, and methods are disclosed.
摘要翻译： 在设备中接收到选通信号，并且当选通信号包括前导码时，设备中的操作的执行被延迟。 公开了附加装置，系统和方法。
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公开(公告)号：US08164375B2
公开(公告)日：2012-04-24
申请号：US12568525
申请日：2009-09-28
申请人： Paul A. LaBerge
发明人： Paul A. LaBerge
IPC分类号： H03K3/00
CPC分类号： G06F1/12
摘要： A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.
摘要翻译： 同步器系统和方法可以与传统的可调节延迟电路一起使用，以便在输出时钟信号之一的可调节延迟电路的时间延迟被改变时，保持不同时钟域的时钟信号之间的伪同步相位关系 。
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