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1.发明申请MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM 有权使用堆叠存储器设备的存储器系统和方法，以及使用存储器系统的系统公开(公告)号：US20110296227A1
公开(公告)日：2011-12-01
申请号：US13209273
申请日：2011-08-12
IPC分类号： G06F1/08
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
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2.发明授权Memory system and method using stacked memory device dice, and system using the memory system 有权内存系统和方法采用堆叠式存储设备骰子，系统采用内存系统公开(公告)号：US08010866B2
公开(公告)日：2011-08-30
申请号：US12961291
申请日：2010-12-06
IPC分类号： H03M13/00
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其它信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
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3.发明授权Memory system and method using stacked memory device dice, and system using the memory system 有权内存系统和方法采用堆叠式存储设备骰子，系统采用内存系统公开(公告)号：US08533416B2
公开(公告)日：2013-09-10
申请号：US13209273
申请日：2011-08-12
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
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4.发明授权Memory system and method using stacked memory device dice, and system using the memory system 有权内存系统和方法采用堆叠式存储设备骰子，系统采用内存系统公开(公告)号：US07855931B2
公开(公告)日：2010-12-21
申请号：US12176951
申请日：2008-07-21
IPC分类号： G11C8/00
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整应用于每个存储器件管芯的相应选通信号（例如读选通信号）的定时来控制读数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
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5.发明申请MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM 有权使用堆叠存储器设备的存储器系统和方法，以及使用存储器系统的系统公开(公告)号：US20100014364A1
公开(公告)日：2010-01-21
申请号：US12176951
申请日：2008-07-21
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
摘要翻译： 存储器系统和方法使用彼此耦合并且耦合到逻辑管芯的堆叠存储器件管芯。 逻辑管芯可以包括定时校正系统，其可操作以控制逻辑管芯从每个存储器件管芯接收诸如读取数据信号的信号的定时。 定时校正通过调整施加到每个存储器件管芯的各个选通信号（例如读取选通信号）的定时来控制读取数据或其他信号的定时。 存储器件芯片可以在由其接收相应的选通信号确定的时间将读取的数据发送到存储器件。 调整每个选通信号的定时，以便同时接收来自所有存储装置芯片的读取数据或其它信号。
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6.发明申请公开(公告)号：US20110075497A1
公开(公告)日：2011-03-31
申请号：US12961291
申请日：2010-12-06
IPC分类号： G11C7/00
CPC分类号： G11C7/1072 , G06F12/00 , G11C5/02 , G11C7/1006 , G11C7/1012 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/222 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/023 , G11C29/028 , G11C2207/107
摘要： A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time.
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7.发明授权Method and apparatus for repairing high capacity/high bandwidth memory devices 有权用于修复高容量/高带宽存储器件的方法和装置公开(公告)号：US08756486B2
公开(公告)日：2014-06-17
申请号：US12166814
申请日：2008-07-02
CPC分类号： G06F11/1092 , G06F11/08 , G06F11/1048 , G11C29/808 , H03M13/09
摘要： Memory systems, systems and methods are described that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.
摘要翻译： 描述了可以包括通过硅通孔彼此连接的多个堆叠的存储器件管芯和逻辑管芯的存储器系统，系统和方法。 一个这样的逻辑管芯包括产生与写入数据相对应的错误检查代码的错误代码生成器。 错误检查码存储在存储器件芯片中，随后与随后从存储器件芯片读取的数据产生的错误校验码进行比较。 在代码不匹配的情况下，可以产生错误信号。 逻辑管芯可能包含一个控制器，用于记录从中读取数据的地址。 控制器或存储器访问设备可以将访问重定向到记录地址处的存储设备裸片。 控制器还可以检查产生误差信号的地址或数据，以识别通孔硅通孔中的故障。
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8.发明申请METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES 有权修复高容量/高带宽存储器件的方法和装置公开(公告)号：US20100005376A1
公开(公告)日：2010-01-07
申请号：US12166814
申请日：2008-07-02
CPC分类号： G06F11/1092 , G06F11/08 , G06F11/1048 , G11C29/808 , H03M13/09
摘要： Memory systems, systems and methods are disclosed that may include a plurality of stacked memory device dice and a logic die connected to each other by through silicon vias. One such logic die includes an error code generator that generates error checking codes corresponding to write data. The error checking codes are stored in the memory device dice and are subsequently compared to error checking codes generated from data subsequently read from the memory device dice. In the event the codes do not match, an error signal can be generated. The logic die may contain a controller that records the address from which the data was read. The controller or memory access device may redirect accesses to the memory device dice at the recorded addresses. The controller can also examine addresses or data resulting in the error signals being generated to identify faults in the through silicon vias.
摘要翻译： 公开了可以包括通过硅通孔彼此连接的多个堆叠的存储器件管芯和逻辑管芯的存储器系统，系统和方法。 一个这样的逻辑管芯包括产生与写入数据相对应的错误检查代码的错误代码生成器。 错误检查码存储在存储器件芯片中，随后与随后从存储器件芯片读取的数据产生的错误校验码进行比较。 在代码不匹配的情况下，可以产生错误信号。 逻辑管芯可能包含一个控制器，用于记录从中读取数据的地址。 控制器或存储器访问设备可以将访问重定向到记录地址处的存储设备裸片。 控制器还可以检查产生误差信号的地址或数据，以识别通孔硅通孔中的故障。
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公开(公告)号：US08938630B2
公开(公告)日：2015-01-20
申请号：US13561632
申请日：2012-07-30
申请人： Joseph M. Jeddeloh
发明人： Joseph M. Jeddeloh
CPC分类号： G11C5/147 , G06F1/3234 , G06F1/329 , G06F3/0631 , G06F9/5083 , G11C7/00 , Y02D10/24
摘要： The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus.
摘要翻译： 本公开包括用于装置功率控制的装置和方法。 多个实施例包括确定准备执行的命令队列中的多个命令中的每一个的功率简档，并且基于命令数量的功率分布来选择命令队列中用于执行的命令数量的一部分 以控制设备中的功率消耗。
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10.发明授权Dynamic synchronization of data capture on an optical or other high speed communications link 有权光学或其他高速通信链路上数据捕获的动态同步公开(公告)号：US08892974B2
公开(公告)日：2014-11-18
申请号：US13470613
申请日：2012-05-14
申请人： Terry R. Lee , Joseph M. Jeddeloh
发明人： Terry R. Lee , Joseph M. Jeddeloh
CPC分类号： H04B10/2504 , H04L1/0001 , H04L1/242 , H04L7/043
摘要： A method that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.
摘要翻译： 一种动态调整通信网络链路控制参数的方法。 通信网络包括通过第一数据链路耦合到接收机的发射机。 发射器和接收器各自具有影响该部件的操作的至少一个相关联的链接控制参数。 根据一种方法，通过第一数据链路传输数据信号，并且捕获发送的数据信号。 将捕获的数据信号的值与这些信号的期望值进行比较，并且调整链路控制参数的值以成功捕获所发送的数字信号。
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