公开(公告)号：US20130173848A1

公开(公告)日：2013-07-04

申请号：US13341579

申请日：2011-12-30

申请人： Paul A. Lassa ,  Robert D. Selinger ,  Alan W. Sinclair

发明人： Paul A. Lassa ,  Robert D. Selinger ,  Alan W. Sinclair

IPC分类号： G06F12/00

CPC分类号： G06F3/0688 ,  G06F3/0619 ,  G06F3/065 ,  G06F11/1072 ,  G11C29/04

摘要： A controller is presented having one or more interfaces through which to communicate with a plurality of memory dies with multi-level memory cells and an interface through which to communicate with a host. The controller also contains a processor that is configured to receive a command from the host to program data in a plurality of lower pages and a plurality of upper pages of the multi-level memory cells. The controller detects an indication from the host that indicates which previously-programmed lower pages from a previous program command are at risk of being corrupted by the programming of the upper pages from the received program command. Prior to programming the upper pages, the controller backs up the previously-programmed lower pages from the previous program command that are at risk of being corrupted but not the lower pages of data programmed by the received program command.

摘要翻译： 呈现具有一个或多个接口的控制器，通过该接口与具有多级存储器单元的多个存储器管芯通信，以及与主机通信的接口。 控制器还包括处理器，其被配置为从主机接收命令以对多级存储器单元的多个较低页面和多个上部页面中的数据进行编程。 控制器检测来自主机的指示，指示来自先前程序命令的哪些先前编程的下部页面有被接收到的程序命令的上位页编程损坏的危险。 在对页面进行编程之前，控制器将从先前编程的下一个程序命令备份，这些页面有被损坏的危险，而不是由接收的程序命令编程的数据的下一页。

公开(公告)号：US09141308B2

公开(公告)日：2015-09-22

申请号：US13341579

申请日：2011-12-30

申请人： Paul A. Lassa ,  Robert D. Selinger ,  Alan W. Sinclair

发明人： Paul A. Lassa ,  Robert D. Selinger ,  Alan W. Sinclair

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/04

CPC分类号： G06F3/0688 ,  G06F3/0619 ,  G06F3/065 ,  G06F11/1072 ,  G11C29/04

摘要： A controller is presented having one or more interfaces through which to communicate with a plurality of memory dies with multi-level memory cells and an interface through which to communicate with a host. The controller also contains a processor that is configured to receive a command from the host to program data in a plurality of lower pages and a plurality of upper pages of the multi-level memory cells. The controller detects an indication from the host that indicates which previously-programmed lower pages from a previous program command are at risk of being corrupted by the programming of the upper pages from the received program command. Prior to programming the upper pages, the controller backs up the previously-programmed lower pages from the previous program command that are at risk of being corrupted but not the lower pages of data programmed by the received program command.

摘要翻译： 呈现具有一个或多个接口的控制器，通过该接口与具有多级存储器单元的多个存储器管芯通信，以及与主机通信的接口。 控制器还包括处理器，其被配置为从主机接收命令以对多级存储器单元的多个较低页面和多个上部页面中的数据进行编程。 控制器检测来自主机的指示，指示来自先前程序命令的哪些先前编程的下部页面有被接收到的程序命令的上位页编程损坏的危险。 在对页面进行编程之前，控制器将从先前编程的下一个程序命令备份，这些页面有被损坏的危险，而不是由接收的程序命令编程的数据的下一页。

公开(公告)号：US20120331207A1

公开(公告)日：2012-12-27

申请号：US13167929

申请日：2011-06-24

申请人： Paul A. Lassa ,  Robert D. Selinger

发明人： Paul A. Lassa ,  Robert D. Selinger

IPC分类号： G06F12/02

CPC分类号： G06F1/3278 ,  G06F1/206 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0688 ,  Y02D10/157 ,  Y02D10/16 ,  Y02D50/20

摘要： The embodiments described herein provide a controller, storage device, and method for power throttling memory operations. In one embodiment, a controller is provided in a storage device with a plurality of flash memory devices. The controller determines how much power will be consumed (or heat will be generated) by each of a plurality of commands and dynamically alters when each of the commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed (or heat will be generated), so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time (or a predetermined temperature). In some embodiments, the storage device also has a thermal sensor, and a reading from the thermal sensor can be used, instead of or in addition to the power or thermal costs of each command, to dynamically alter when the commands are performed.

摘要翻译： 这里描述的实施例提供了用于功率节流存储器操作的控制器，存储设备和方法。 在一个实施例中，在具有多个闪存器件的存储设备中提供控制器。 控制器确定由多个命令中的每个命令消耗多少功率（或产生热量），并且当基于多少的确定来执行在一个或多个闪存设备上操作的每个命令时执行动态改变 电力将被消耗（或将产生热量），使得多个命令的执行在一段时间（或预定温度）内不超过预定的平均功率限制。 在一些实施例中，存储装置还具有热传感器，并且可以使用来自热传感器的读取来代替或补充每个命令的功率或热成本，以便在执行命令时动态地改变。

公开(公告)号：US08694719B2

公开(公告)日：2014-04-08

申请号：US13167929

申请日：2011-06-24

申请人： Paul A. Lassa ,  Robert D. Selinger

发明人： Paul A. Lassa ,  Robert D. Selinger

IPC分类号： G06F12/00

CPC分类号： G06F1/3278 ,  G06F1/206 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0688 ,  Y02D10/157 ,  Y02D10/16 ,  Y02D50/20

摘要： The embodiments described herein provide a controller, storage device, and method for power throttling memory operations. In one embodiment, a controller is provided in a storage device with a plurality of flash memory devices. The controller determines how much power will be consumed (or heat will be generated) by each of a plurality of commands and dynamically alters when each of the commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed (or heat will be generated), so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time (or a predetermined temperature). In some embodiments, the storage device also has a thermal sensor, and a reading from the thermal sensor can be used, instead of or in addition to the power or thermal costs of each command, to dynamically alter when the commands are performed.

摘要翻译： 这里描述的实施例提供了用于功率节流存储器操作的控制器，存储设备和方法。 在一个实施例中，在具有多个闪存器件的存储设备中提供控制器。 控制器确定由多个命令中的每个命令消耗多少功率（或产生热量），并且当基于多少的确定来执行在一个或多个闪存设备上操作的每个命令时执行动态改变 电力将被消耗（或将产生热量），使得多个命令的执行在一段时间（或预定温度）内不超过预定的平均功率限制。 在一些实施例中，存储装置还具有热传感器，并且可以使用来自热传感器的读取来代替或补充每个命令的功率或热成本，以便在执行命令时动态地改变。

公开(公告)号：US09116620B2

公开(公告)日：2015-08-25

申请号：US13341443

申请日：2011-12-30

申请人： Paul A. Lassa ,  Robert D. Selinger

发明人： Paul A. Lassa ,  Robert D. Selinger

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F12/10 ,  G06F12/02

CPC分类号： G06F3/0607 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F2212/7208

摘要： A controller and method for memory aliasing for different flash memory types are presented. In one embodiment, a controller is presented having one or more interfaces through which to communicate with a plurality of memory dies, wherein at least one of the memory dies is of a different memory type than the other memory dies. The controller also has an interface through which to communicate with a host, wherein the interface only supports commands for a single memory types. The controller further contains a processor that is configured to receive a logical address and a command from the host, determine which memory die is associated with the logical address, and translate the command received from the host to a form suitable for the memory type of the memory die associated with the logical address.

摘要翻译： 提出了一种用于不同闪存类型的存储器混叠的控制器和方法。 在一个实施例中，呈现具有一个或多个接口以与多个存储器管芯通信的控制器，其中至少一个存储器管芯具有与其它存储器管芯不同的存储器类型。 控制器还具有与主机通信的接口，其中接口仅支持单个存储器类型的命令。 控制器还包括处理器，其被配置为从主机接收逻辑地址和命令，确定哪个存储器管芯与逻辑地址相关联，并且将从主机接收到的命令转换成适合于存储器类型的形式 与逻辑地址相关联的存储器管芯。

公开(公告)号：US20130173846A1

公开(公告)日：2013-07-04

申请号：US13341443

申请日：2011-12-30

申请人： Paul A. Lassa ,  Robert D. Selinger

发明人： Paul A. Lassa ,  Robert D. Selinger

IPC分类号： G06F12/00

CPC分类号： G06F3/0607 ,  G06F3/0659 ,  G06F3/0661 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1081 ,  G06F2212/7208

摘要： A controller and method for memory aliasing for different flash memory types are presented. In one embodiment, a controller is presented having one or more interfaces through which to communicate with a plurality of memory dies, wherein at least one of the memory dies is of a different memory type than the other memory dies. The controller also has an interface through which to communicate with a host, wherein the interface only supports commands for a single memory types. The controller further contains a processor that is configured to receive a logical address and a command from the host, determine which memory die is associated with the logical address, and translate the command received from the host to a form suitable for the memory type of the memory die associated with the logical address.

摘要翻译： 提出了一种用于不同闪存类型的存储器混叠的控制器和方法。 在一个实施例中，呈现具有一个或多个接口以与多个存储器管芯通信的控制器，其中至少一个存储器管芯具有与其它存储器管芯不同的存储器类型。 控制器还具有与主机通信的接口，其中接口仅支持单个存储器类型的命令。 控制器还包括处理器，其被配置为从主机接收逻辑地址和命令，确定哪个存储器管芯与逻辑地址相关联，并且将从主机接收到的命令转换成适合于存储器类型的形式 与逻辑地址相关联的存储器管芯。

公开(公告)号：US08700961B2

公开(公告)日：2014-04-15

申请号：US13330975

申请日：2011-12-20

申请人： Paul A. Lassa ,  Alan W. Sinclair

发明人： Paul A. Lassa ,  Alan W. Sinclair

IPC分类号： G11C29/00

CPC分类号： G06F12/0246 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/1016 ,  G06F2212/7208 ,  G11C29/883

摘要： A controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies, each having a respective plurality of memory blocks, some of which are good and some of which are bad. The controller determines a number of good blocks in each memory die. Based on the determined number of good blocks in each memory die, the controller selects a memory die from each of the multi-chip memory packages to access in parallel, wherein the selected memory dies are not necessarily all in the same relative position in each multi-chip package. The controller then creates a metablock from a set of good blocks from each of the selected memory dies, wherein a maximum number of metablocks that can be created across the selected memory dies is determined by a lowest number of good blocks in the selected memory dies.

摘要翻译： 控制器与多个多芯片存储器包进行通信。 每个多芯片存储器封装包括多个存储器管芯，每个存储器管芯具有相应的多个存储器块，其中一些存储器块是好的，其中一些是不好的。 控制器确定每个存储器管芯中的多个好的块。 基于每个存储器管芯中所确定的良好块的数量，控制器从每个多芯片存储器封装中选择并行访问的存储器管芯，其中所选择的存储器管芯不一定在每个多个存储器管芯中处于相同的相对位置 芯片封装 然后，控制器从来自所选择的每个存储器管芯的一组好的块中创建一个元区块，其中可以通过所选择的存储器管芯中的最低数量的好块来确定跨所选择的存储器管芯可以创建的最大数量的元区块。

公开(公告)号：US20130159601A1

公开(公告)日：2013-06-20

申请号：US13330975

申请日：2011-12-20

申请人： Paul A. Lassa ,  Alan W. Sinclair

发明人： Paul A. Lassa ,  Alan W. Sinclair

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/1016 ,  G06F2212/7208 ,  G11C29/883

摘要： A controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies, each having a respective plurality of memory blocks, some of which are good and some of which are bad. The controller determines a number of good blocks in each memory die. Based on the determined number of good blocks in each memory die, the controller selects a memory die from each of the multi-chip memory packages to access in parallel, wherein the selected memory dies are not necessarily all in the same relative position in each multi-chip package. The controller then creates a metablock from a set of good blocks from each of the selected memory dies, wherein a maximum number of metablocks that can be created across the selected memory dies is determined by a lowest number of good blocks in the selected memory dies.

摘要翻译： 控制器与多个多芯片存储器包进行通信。 每个多芯片存储器封装包括多个存储器管芯，每个存储器管芯具有相应的多个存储器块，其中一些存储器块是好的，其中一些是不好的。 控制器确定每个存储器管芯中的多个好的块。 基于每个存储器管芯中所确定的良好块的数量，控制器从每个多芯片存储器封装中选择并行访问的存储器管芯，其中所选择的存储器管芯不一定在每个多个存储器管芯中处于相同的相对位置 芯片封装 然后，控制器从来自所选择的存储器管芯的每一个的一组好的块创建元区块，其中可以通过所选择的存储器管芯中的最低数量的好块来确定跨所选择的存储器管芯可以创建的最大数量的元区块。

公开(公告)号：US20120173792A1

公开(公告)日：2012-07-05

申请号：US12982833

申请日：2010-12-30

申请人： Paul A. Lassa ,  David C. Brief

发明人： Paul A. Lassa ,  David C. Brief

IPC分类号： G06F12/00

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4843 ,  G06F12/0246 ,  G06F2003/0691 ,  G06F2003/0697

摘要： The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.

摘要翻译： 这里描述的实施例提供了一种用于执行后台命令或操作的控制器和方法。 在一个实施例中，控制器设置有与主机和多个闪存设备通信的接口。 控制器包含一个可执行从主机接收的前景指令的处理器，其中处理器执行前台命令以完成而不中断。 处理器还可操作以执行存储在控制器的存储器中的后台命令或操作，其中处理器执行后台命令，直到由前台命令完成或抢占。 如果后台命令被抢占，则处理器可以在稍后时间恢复执行后台命令，直到完成。

公开(公告)号：US07928746B1

公开(公告)日：2011-04-19

申请号：US11966147

申请日：2007-12-28

申请人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

发明人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

IPC分类号： G01R31/3187

CPC分类号： G01R31/2884 ,  G01R31/318511 ,  G01R31/318558 ,  G01R31/31924

摘要： A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.

摘要翻译： 一种多接口集成电路，其中在芯片使用寿命期间，一次只有一个接口处于活动状态。 但是，特殊的测试逻辑可以一次启动所有片上接口模块，从而可以执行完整的测试周期。 所有接口都在一个测试程序中执行。 由于某些接口模式下某些焊盘无效，因此使用掩码位来选择在哪个测试周期内监视哪些焊盘。