公开(公告)号：US20120173792A1

公开(公告)日：2012-07-05

申请号：US12982833

申请日：2010-12-30

申请人： Paul A. Lassa ,  David C. Brief

发明人： Paul A. Lassa ,  David C. Brief

IPC分类号： G06F12/00

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4843 ,  G06F12/0246 ,  G06F2003/0691 ,  G06F2003/0697

摘要： The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.

摘要翻译： 这里描述的实施例提供了一种用于执行后台命令或操作的控制器和方法。 在一个实施例中，控制器设置有与主机和多个闪存设备通信的接口。 控制器包含一个可执行从主机接收的前景指令的处理器，其中处理器执行前台命令以完成而不中断。 处理器还可操作以执行存储在控制器的存储器中的后台命令或操作，其中处理器执行后台命令，直到由前台命令完成或抢占。 如果后台命令被抢占，则处理器可以在稍后时间恢复执行后台命令，直到完成。

公开(公告)号：US07928746B1

公开(公告)日：2011-04-19

申请号：US11966147

申请日：2007-12-28

申请人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

发明人： Po-Shen Lai ,  Paul A. Lassa ,  Paul C. Paternoster

IPC分类号： G01R31/3187

CPC分类号： G01R31/2884 ,  G01R31/318511 ,  G01R31/318558 ,  G01R31/31924

摘要： A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.

摘要翻译： 一种多接口集成电路，其中在芯片使用寿命期间，一次只有一个接口处于活动状态。 但是，特殊的测试逻辑可以一次启动所有片上接口模块，从而可以执行完整的测试周期。 所有接口都在一个测试程序中执行。 由于某些接口模式下某些焊盘无效，因此使用掩码位来选择在哪个测试周期内监视哪些焊盘。

公开(公告)号：US08700961B2

公开(公告)日：2014-04-15

申请号：US13330975

申请日：2011-12-20

申请人： Paul A. Lassa ,  Alan W. Sinclair

发明人： Paul A. Lassa ,  Alan W. Sinclair

IPC分类号： G11C29/00

CPC分类号： G06F12/0246 ,  G06F3/0613 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/1016 ,  G06F2212/7208 ,  G11C29/883

摘要： A controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies, each having a respective plurality of memory blocks, some of which are good and some of which are bad. The controller determines a number of good blocks in each memory die. Based on the determined number of good blocks in each memory die, the controller selects a memory die from each of the multi-chip memory packages to access in parallel, wherein the selected memory dies are not necessarily all in the same relative position in each multi-chip package. The controller then creates a metablock from a set of good blocks from each of the selected memory dies, wherein a maximum number of metablocks that can be created across the selected memory dies is determined by a lowest number of good blocks in the selected memory dies.

摘要翻译： 控制器与多个多芯片存储器包进行通信。 每个多芯片存储器封装包括多个存储器管芯，每个存储器管芯具有相应的多个存储器块，其中一些存储器块是好的，其中一些是不好的。 控制器确定每个存储器管芯中的多个好的块。 基于每个存储器管芯中所确定的良好块的数量，控制器从每个多芯片存储器封装中选择并行访问的存储器管芯，其中所选择的存储器管芯不一定在每个多个存储器管芯中处于相同的相对位置 芯片封装 然后，控制器从来自所选择的每个存储器管芯的一组好的块中创建一个元区块，其中可以通过所选择的存储器管芯中的最低数量的好块来确定跨所选择的存储器管芯可以创建的最大数量的元区块。

公开(公告)号：US20130265825A1

公开(公告)日：2013-10-10

申请号：US13443404

申请日：2012-04-10

申请人： Paul A. Lassa

发明人： Paul A. Lassa

IPC分类号： G11C16/04

CPC分类号： G06F3/0688 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0649 ,  G06F3/0655 ,  G06F3/0685

摘要： In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP.

摘要翻译： 在诸如固态盘（SSD）的存储设备中，中央控制器与多个多芯片存储器封装通信。 每个多芯片存储器包包括多个存储器管芯和本地处理器，其中所述多个存储器管芯包括不同的存储器层。 中央控制器可以处理虚拟地址空间的管理，而每个MCP中的本地处理器管理其各自MCP的存储器管芯内的存储器层内的数据的存储。

公开(公告)号：US08102062B1

公开(公告)日：2012-01-24

申请号：US11966012

申请日：2007-12-28

申请人： Paul A. Lassa ,  Paul C. Paternoster ,  Po-Shen Lai

发明人： Paul A. Lassa ,  Paul C. Paternoster ,  Po-Shen Lai

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L23/49855 ,  H01L23/50 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06155 ,  H01L2224/06515 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Methods and systems for forming a variety of integrated circuits, having quite different interfaces and packages, from a single manufactured die. Preferably the die has bond pads for at least a first mode of operation positioned along only two of its four sides, and these bond pads are sufficient to construct a multi-chip module in which the die is functional in the first mode of operation. Many of the pads on these two sides are duplicated on third and/or fourth sides, except that power management circuitry prevents wasteful capacitive current onto whichever of the duplicated pads is not connected out. Optionally the third and/or fourth sides can be used for connections needed for a mode which is not available with two sides only.

摘要翻译： 用于从单个制造的模具形成具有完全不同的界面和封装的各种集成电路的方法和系统。 优选地，管芯具有至少第一操作模式的接合焊盘，其仅沿着其四个侧面中的两个定位，并且这些接合焊盘足以构造其中裸片在第一操作模式中起作用的多芯片模块。 除了电源管理电路防止浪费的电容电流到无连接的重叠焊盘之外，这两侧的许多焊盘在第三和/或第四侧都被复制。 可选地，第三和/或第四侧可以用于仅在两侧不可用的模式所需的连接。

公开(公告)号：US08819328B2

公开(公告)日：2014-08-26

申请号：US12982833

申请日：2010-12-30

申请人： Paul A. Lassa ,  David C. Brief

发明人： Paul A. Lassa ,  David C. Brief

IPC分类号： G06F12/00 ,  G06F9/48 ,  G06F3/06 ,  G06F12/02

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4843 ,  G06F12/0246 ,  G06F2003/0691 ,  G06F2003/0697

摘要： The embodiments described herein provide a controller and method for performing a background commands or operations. In one embodiment, a controller is provided with interfaces through which to communicate with a host and a plurality of flash memory devices. The controller contains a processor operative to perform a foreground command received from the host, wherein the processor performs the foreground command to completion without interruption. The processor is also operative to perform a background commands or operations stored in the controller's memory, wherein the processor performs the background command until completed or preempted by a foreground command. If the background command is preempted, the processor can resume performing the background command at a later time until completed.

摘要翻译： 这里描述的实施例提供了一种用于执行后台命令或操作的控制器和方法。 在一个实施例中，控制器设置有与主机和多个闪存设备通信的接口。 控制器包含一个可执行从主机接收的前景指令的处理器，其中处理器执行前台命令以完成而不中断。 处理器还可操作以执行存储在控制器的存储器中的后台命令或操作，其中处理器执行后台命令，直到由前台命令完成或抢占。 如果后台命令被抢占，则处理器可以在稍后时间恢复执行后台命令，直到完成。

公开(公告)号：US08694719B2

公开(公告)日：2014-04-08

申请号：US13167929

申请日：2011-06-24

申请人： Paul A. Lassa ,  Robert D. Selinger

发明人： Paul A. Lassa ,  Robert D. Selinger

IPC分类号： G06F12/00

CPC分类号： G06F1/3278 ,  G06F1/206 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0688 ,  Y02D10/157 ,  Y02D10/16 ,  Y02D50/20

摘要： The embodiments described herein provide a controller, storage device, and method for power throttling memory operations. In one embodiment, a controller is provided in a storage device with a plurality of flash memory devices. The controller determines how much power will be consumed (or heat will be generated) by each of a plurality of commands and dynamically alters when each of the commands operating on one or more of the flash memory devices is performed based on the determination of how much power would be consumed (or heat will be generated), so that performance of the plurality of commands does not exceed a predetermined average power limit over a period of time (or a predetermined temperature). In some embodiments, the storage device also has a thermal sensor, and a reading from the thermal sensor can be used, instead of or in addition to the power or thermal costs of each command, to dynamically alter when the commands are performed.

摘要翻译： 这里描述的实施例提供了用于功率节流存储器操作的控制器，存储设备和方法。 在一个实施例中，在具有多个闪存器件的存储设备中提供控制器。 控制器确定由多个命令中的每个命令消耗多少功率（或产生热量），并且当基于多少的确定来执行在一个或多个闪存设备上操作的每个命令时执行动态改变 电力将被消耗（或将产生热量），使得多个命令的执行在一段时间（或预定温度）内不超过预定的平均功率限制。 在一些实施例中，存储装置还具有热传感器，并且可以使用来自热传感器的读取来代替或补充每个命令的功率或热成本，以便在执行命令时动态地改变。

公开(公告)号：US20130173848A1

公开(公告)日：2013-07-04

申请号：US13341579

申请日：2011-12-30

申请人： Paul A. Lassa ,  Robert D. Selinger ,  Alan W. Sinclair

发明人： Paul A. Lassa ,  Robert D. Selinger ,  Alan W. Sinclair

IPC分类号： G06F12/00

CPC分类号： G06F3/0688 ,  G06F3/0619 ,  G06F3/065 ,  G06F11/1072 ,  G11C29/04

摘要： A controller is presented having one or more interfaces through which to communicate with a plurality of memory dies with multi-level memory cells and an interface through which to communicate with a host. The controller also contains a processor that is configured to receive a command from the host to program data in a plurality of lower pages and a plurality of upper pages of the multi-level memory cells. The controller detects an indication from the host that indicates which previously-programmed lower pages from a previous program command are at risk of being corrupted by the programming of the upper pages from the received program command. Prior to programming the upper pages, the controller backs up the previously-programmed lower pages from the previous program command that are at risk of being corrupted but not the lower pages of data programmed by the received program command.

摘要翻译： 呈现具有一个或多个接口的控制器，通过该接口与具有多级存储器单元的多个存储器管芯通信，以及与主机通信的接口。 控制器还包括处理器，其被配置为从主机接收命令以对多级存储器单元的多个较低页面和多个上部页面中的数据进行编程。 控制器检测来自主机的指示，指示来自先前程序命令的哪些先前编程的下部页面有被接收到的程序命令的上位页编程损坏的危险。 在对页面进行编程之前，控制器将从先前编程的下一个程序命令备份，这些页面有被损坏的危险，而不是由接收的程序命令编程的数据的下一页。

公开(公告)号：US20130173842A1

公开(公告)日：2013-07-04

申请号：US13338941

申请日：2011-12-28

申请人： King Ying Ng ,  Marielle Bundukin ,  Paul A. Lassa ,  Sergey A. Gorobets ,  Liam Parker

发明人： King Ying Ng ,  Marielle Bundukin ,  Paul A. Lassa ,  Sergey A. Gorobets ,  Liam Parker

IPC分类号： G06F12/00

CPC分类号： G06F12/0246

摘要： A method and system are disclosed for controlling the storage of data in a storage device to reduce fragmentation. The method may include a controller of a storage device receiving data for storage in non-volatile memory and determining if a threshold amount of data has been received. When the threshold amount of data is received, the non-volatile memory is scanned for sequentially numbered logical groups of data previously written in noncontiguous locations in the non-volatile memory. When a threshold amount of such sequentially numbered logical groups is found, the controller re-writes the sequentially numbered logical groups of data contiguously into a new block. The system may include a storage device with a controller configured to perform the method noted above, where the thresholds for scanning the memory for fragmented data and removing fragmentation by re-writing the fragmented data into new blocks may be fixed or variable.

摘要翻译： 公开了一种用于控制存储设备中的数据存储以减少碎片的方法和系统。 该方法可以包括存储设备的控制器，其接收用于存储在非易失性存储器中的数据并且确定是否已经接收到阈值量的数据。 当接收到阈值数据量时，扫描非易失性存储器，以便先前写入非易失性存储器中的不连续位置的顺序编号的数据逻辑组的数据。 当发现这种顺序编号的逻辑组的阈值量时，控制器将顺序编号的逻辑数据组重新写入到新的块中。 该系统可以包括具有被配置为执行上述方法的控制器的存储设备，其中用于扫描存储器用于分段数据并通过将分段数据重新写入新块来去除分段的阈值可以是固定的或可变的。

公开(公告)号：US08760922B2

公开(公告)日：2014-06-24

申请号：US13443404

申请日：2012-04-10

申请人： Paul A. Lassa

发明人： Paul A. Lassa

IPC分类号： G11C11/34

CPC分类号： G06F3/0688 ,  G06F3/0614 ,  G06F3/0619 ,  G06F3/0649 ,  G06F3/0655 ,  G06F3/0685

摘要： In a storage device such as a solid state disk (SSD), a central controller communicates with a plurality of multi-chip memory packages. Each multi-chip memory package comprises a plurality of memory dies and a local processor, wherein the plurality of memory dies includes different memory tiers. The central controller may handle management of the virtual address space while the local processor in each MCP manages the storage of data within memory tiers in the memory dies of its respective MCP.

摘要翻译： 在诸如固态盘（SSD）的存储设备中，中央控制器与多个多芯片存储器封装通信。 每个多芯片存储器包包括多个存储器管芯和本地处理器，其中所述多个存储器管芯包括不同的存储器层。 中央控制器可以处理虚拟地址空间的管理，而每个MCP中的本地处理器管理其各自MCP的存储器管芯内的存储器层内的数据的存储。