公开(公告)号：US20050156234A1

公开(公告)日：2005-07-21

申请号：US10977732

申请日：2004-10-29

申请人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

发明人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

IPC分类号： H01L21/336 ,  H01L29/40 ,  H01L29/41 ,  H01L29/76 ,  H01L29/78 ,  H01L31/113

CPC分类号： H01L29/402 ,  H01L29/41 ,  H01L29/7835

摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A drift region is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on at least a portion of the upper surface of the semiconductor layer and above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the first and second source/drain regions. The MOS device further includes a shielding structure formed on the insulating layer above at least a portion of the drift region. The shielding structure is configured such that an amount of hot carrier injection degradation in the MOS device is controlled as a function of an amount of coverage of the shielding structure over an upper surface of the drift region.

摘要翻译： 形成MOS器件，其包括第一导电类型的半导体层，以及形成在靠近半导体层的上表面的半导体层中的第二导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域 相对于彼此间隔开。 在靠近半导体层的上表面的半导体层中至少部分地在第一和第二源/漏区之间形成漂移区。 绝缘层形成在半导体层的上表面的至少一部分上方和漂移区的至少一部分上方。 栅极形成在绝缘层上并且至少部分地在第一和第二源/漏区之间。 MOS器件还包括形成在漂移区的至少一部分上方的绝缘层上的屏蔽结构。 屏蔽结构被配置为使得MOS器件中的热载流子注入劣化量被控制为在漂移区域的上表面上的屏蔽结构的覆盖量的函数。

公开(公告)号：US20080003703A1

公开(公告)日：2008-01-03

申请号：US11853417

申请日：2007-09-11

申请人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

发明人： Peter Gammel ,  Isik Kizilyalli ,  Marco Mastrapasqua ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

IPC分类号： H01L21/66

CPC分类号： H01L29/402 ,  H01L29/41 ,  H01L29/7835

摘要： In a metal-oxide semiconductor device including first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, a drift region formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, an insulating layer formed on at least a portion of the upper surface of the semiconductor layer, and a gate formed on the insulating layer and at least partially between the first and second source/drain regions, a method for controlling an amount of hot carrier injection degradation in the device includes the steps of: forming a shielding structure on the insulating layer above at least a portion of the drift region and substantially between the gate and the second source/drain region; and adjusting an amount of coverage of the shielding structure over an upper surface of the drift region so as to minimize the amount of hot-carrier injection degradation while maintaining a breakdown voltage in the device which is greater than or equal to a prescribed value.

摘要翻译： 在包括形成在靠近半导体层的上表面的第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域的金属氧化物半导体器件中，形成在靠近上部的半导体层中的漂移区域 半导体层的表面，并且至少部分地在第一和第二源极/漏极区之间，形成在半导体层的上表面的至少一部分上的绝缘层和形成在绝缘层上的栅极，并且至少部分地在第一和/ 第一和第二源极/漏极区域，用于控制器件中热载流子注入劣化量的方法包括以下步骤：在绝缘层上形成屏蔽结构，该屏蔽结构位于漂移区域的至少一部分上方并且基本上在栅极 和第二源极/漏极区域; 以及调整所述屏蔽结构在所述漂移区域的上表面上的覆盖范围，以便在保持所述器件中的击穿电压大于或等于规定值的同时使热载流子注入劣化的量最小化。

公开(公告)号：US20050110083A1

公开(公告)日：2005-05-26

申请号：US10719197

申请日：2003-11-21

申请人： Peter Gammel ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

发明人： Peter Gammel ,  Muhammed Shibib ,  Zhijian Xie ,  Shuming Xu

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L29/7801 ,  H01L21/823481 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/7835

摘要： An MOS device comprises a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced laterally apart relative to one another and are formed in an active region of the semiconductor layer. The MOS device further comprises a gate formed above the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The gate is configured such that a dimension of the gate, defined substantially parallel to at least one of the first and second source/drain regions, is confined to be substantially within the active region of the device. An isolation structure is formed in the semiconductor layer, the isolation structure being configured to substantially isolate the first source/drain region from the second source/drain region.

摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。 第一和第二源极/漏极区域相对于彼此横向间隔开，并且形成在半导体层的有源区中。 MOS器件还包括形成在半导体层上方的接近半导体层的上表面并且至少部分地在第一和第二源极/漏极区之间的栅极。 栅极被配置为使得基本上平行于第一和第二源极/漏极区域中的至少一个限定的栅极的尺寸被限制为基本上位于器件的有源区域内。 在半导体层中形成隔离结构，隔离结构被配置为使第一源极/漏极区域与第二源极/漏极区域基本上隔离。

公开(公告)号：US20080054994A1

公开(公告)日：2008-03-06

申请号：US11927950

申请日：2007-10-30

申请人： Muhammed Shibib ,  Shuming Xu

发明人： Muhammed Shibib ,  Shuming Xu

IPC分类号： G05F1/10 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/402 ,  H01L29/7831

摘要： An MOS device includes first and second source/drain regions of a first conductivity type formed in a semiconductor layer of a second conductivity type proximate an upper surface of the semiconductor layer, the first and second source/drain regions being spaced apart relative to one another. A non-uniformly doped channel region of the first conductivity type is formed in the semiconductor layer proximate the upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. An insulating layer is formed on the upper surface of the semiconductor layer. A first gate is formed on the insulating layer at least partially between the first and second source/drain regions and above at least a portion of the channel region, and at least a second gate formed on the insulating layer above at least a portion of the channel region and between the first gate and the second source/drain region. The second gate has a length which is substantially greater than a length of the first gate, the first and second gates being electrically isolated from one another.

摘要翻译： MOS器件包括在半导体层的上表面附近形成在第二导电类型的半导体层中的第一导电类型的第一和第二源极/漏极区域，第一和第二源极/漏极区域相对于彼此间隔开 。 第一导电类型的非均匀掺杂沟道区形成在靠近半导体层的上表面的半导体层中，并且至少部分地在第一和第二源/漏区之间。 绝缘层形成在半导体层的上表面上。 至少部分地在第一和第二源极/漏极区域之间并且在沟道区域的至少一部分上方形成第一栅极，并且至少在绝缘层上形成的至少一部分第二栅极 并且在第一栅极和第二源极/漏极区域之间。 第二栅极的长度远大于第一栅极的长度，第一栅极和第二栅极彼此电隔离。

公开(公告)号：US20060071270A1

公开(公告)日：2006-04-06

申请号：US10953018

申请日：2004-09-29

申请人： Muhammed Shibib ,  Shuming Xu

发明人： Muhammed Shibib ,  Shuming Xu

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/223 ,  H01L21/2253 ,  H01L21/266 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0886 ,  H01L29/1037 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的靠近半导体层的上表面的第二导电类型的第一和第二源极/漏极区域。 第一和第二源极/漏极区域相对于彼此间隔开。 至少部分地在第一和第二源极/漏极区之间形成栅极，并与半导体层电隔离。 第一和第二源极/漏极区域中的至少一个被配置为具有基本上大于半导体层和给定源极/漏极区域之间的结的宽度的有效宽度。

公开(公告)号：US20050285189A1

公开(公告)日：2005-12-29

申请号：US10878857

申请日：2004-06-28

申请人： Muhammed Shibib ,  Shuming Xu

发明人： Muhammed Shibib ,  Shuming Xu

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7816 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7802 ,  H01L29/7835

摘要： An MOS device comprises a semiconductor layer of a first conductivity type and source and drain regions of a second conductivity type formed in the semiconductor layer, the source and drain regions being spaced apart from one another. A drift region is formed in the semiconductor layer proximate an upper surface of the semiconductor layer and between the source and drain regions, and a insulating layer is formed on the semiconductor layer above at least a portion of the drift region. A gate is formed on the insulating layer and at least partially between the source and drift regions. The MOS device further includes a conductive structure comprising a first end formed on the insulating layer and spaced apart from the gate, and a second end formed on the insulating layer and extending laterally toward the drain region above at least a portion of the drift region. The conductive structure is configured such that a thickness of the insulating layer under the second end of the conductive structure increases as the second end extends toward the drain region.

摘要翻译： MOS器件包括第一导电类型的半导体层和形成在半导体层中的第二导电类型的源区和漏区，源极和漏极彼此间隔开。 在半导体层中，靠近半导体层的上表面并且在源极和漏极区之间形成漂移区，并且在漂移区的至少一部分上方的半导体层上形成绝缘层。 栅极形成在绝缘层上并且至少部分地在源极和漂移区域之间。 MOS器件还包括导电结构，该导电结构包括形成在绝缘层上并与栅极隔开的第一端，以及形成在绝缘层上并在漂移区的至少一部分上方向漏极区横向延伸的第二端。 导电结构被构造成使得当导电结构的第二端下方的绝缘层的厚度随着第二端向漏极区延伸而增加。

公开(公告)号：US20050191815A1

公开(公告)日：2005-09-01

申请号：US11116903

申请日：2005-04-28

申请人： Muhammed Shibib ,  Shuming Xu

发明人： Muhammed Shibib ,  Shuming Xu

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L23/58 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/402 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/7835

摘要： An MOS device includes a semiconductor layer of a first conductivity type, a source region of a second conductivity type formed in the semiconductor layer, and a drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the source region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the source and drain regions. The MOS device further includes a buried LDD region of the second conductivity type formed in the semiconductor layer between the gate and the drain region, the buried LDD region being spaced laterally from the drain region, and a second LDD region of the first conductivity type formed in the buried LDD region and proximate the upper surface of the semiconductor layer. The second LDD region is self-aligned with the gate and spaced laterally from the gate such that the gate is non-overlapping relative to the second LDD region.

公开(公告)号：US20050077552A1

公开(公告)日：2005-04-14

申请号：US10673539

申请日：2003-09-29

申请人： Frank Baiocchi ,  Bailey Jones ,  Muhammed Shibib ,  Shuming Xu

发明人： Frank Baiocchi ,  Bailey Jones ,  Muhammed Shibib ,  Shuming Xu

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L29/0847 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/456

摘要： An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.

摘要翻译： 形成MOS器件，其包括形成在半导体层中的第一导电类型的半导体层，第二导电类型的第一源极/漏极区域和形成在半导体层中的第二导电类型的第二源极/漏极区域，以及 与第一源极/漏极区间隔开。 栅极形成在半导体层的上表面附近并且至少部分地形成在第一和第二源/漏区之间。 所述MOS器件还包括至少一个触点，所述至少一个触点包括在所述第一源极/漏极区域的至少一部分上形成并且与所述第一源极/漏极区域的至少一部分电连接的硅化物层，所述硅化物层从所述栅极横向延伸。 触点还包括直接形成在硅化物层上的至少一个绝缘层。

公开(公告)号：US20060128085A1

公开(公告)日：2006-06-15

申请号：US11348597

申请日：2006-02-07

申请人： Muhammed Shibib ,  Shuming Xu

发明人： Muhammed Shibib ,  Shuming Xu

IPC分类号： H01L21/8234 ,  H01L21/332

CPC分类号： H01L29/0634 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/7816 ,  H01L29/7835

摘要： A method for forming a MOS device includes the steps of forming a gate proximate an upper surface of a semiconductor layer, the semiconductor layer including a substrate of a first conductivity type and a second layer of a second conductivity type; forming first and second source/drain regions of the second conductivity type in the second layer proximate the upper surface of the second layer, the first source/drain region being spaced laterally from the second source/drain region, the gate being formed at least partially between the first and second source/drain regions; and forming at least one electrically conductive trench in the second layer between the gate and the second source/drain region, the trench being formed proximate the upper surface of the semiconductor layer and extending substantially vertically through the second layer to the substrate. The step of forming the trench includes the steps of forming an insulating layer substantially lining sidewalls of the trench, and substantially filling the trench with an electrically conductive material.

摘要翻译： 一种用于形成MOS器件的方法包括以下步骤：在半导体层的上表面附近形成栅极，所述半导体层包括第一导电类型的衬底和第二导电类型的第二层; 在靠近第二层的上表面的第二层中形成第二导电类型的第一和第二源极/漏极区域，第一源极/漏极区域与第二源极/漏极区域横向间隔开，栅极至少部分地形成 在第一和第二源/漏区之间; 以及在所述栅极和所述第二源极/漏极区域之间的所述第二层中形成至少一个导电沟槽，所述沟槽形成在所述半导体层的所述上表面附近并且基本上垂直延伸穿过所述第二层到所述衬底。 形成沟槽的步骤包括以下步骤：形成基本上衬有沟槽侧壁的绝缘层，并用导电材料基本上填充沟槽。

公开(公告)号：US20050221563A1

公开(公告)日：2005-10-06

申请号：US10814062

申请日：2004-03-31

申请人： Frank Baiocchi ,  Bailey Jones ,  Muhammed Shibib ,  Shuming Xu

发明人： Frank Baiocchi ,  Bailey Jones ,  Muhammed Shibib ,  Shuming Xu

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/417

CPC分类号： H01L29/66659 ,  H01L29/4175

摘要： A technique for forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on a least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench in an upper surface of the semiconductor wafer and partially into the epitaxial layer. The method further includes the step of forming at least one diffusion region between a bottom wall of the trench and the substrate, the diffusion region providing an electrical path between the bottom wall of the trench and the substrate. One or more sidewalls of the trench are doped with a first impurity of a known concentration level so as to form an electrical path between an upper surface of the epitaxial layer and the at least one diffusion region. The trench is then filled with a filler material.

摘要翻译： 在半导体晶片中形成半导体结构的技术包括以下步骤：在第一导电类型的半导体衬底的至少一部分上形成外延层，并在半导体晶片的上表面中形成至少一个沟槽，并部分地形成 外延层。 该方法还包括在沟槽的底壁和衬底之间形成至少一个扩散区域的步骤，扩散区域在沟槽的底壁和衬底之间提供电路径。 掺杂具有已知浓度水平的第一杂质的沟槽的一个或多个侧壁，以便在外延层的上表面和至少一个扩散区之间形成电路径。 然后用填充材料填充沟槽。