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公开(公告)号：US07209503B1
公开(公告)日：2007-04-24
申请号：US10838671
申请日：2004-05-03
IPC分类号： H01S5/00
CPC分类号： H01L27/1446 , H01L27/146
摘要： An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.
摘要翻译： 集成电路通过将形成为接收电源电压的PMOS晶体管的p +源极区域等导电区域暴露于来自光源的光能来供电。 导电区域用作通过光电效应在导电区域上产生电压的光电二极管。
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公开(公告)号：US07113427B1
公开(公告)日：2006-09-26
申请号：US11076711
申请日：2005-03-09
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L29/7881
摘要： NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.
摘要翻译： 用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。 可以选择先将电压降低，然后关闭通道上的电压。
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公开(公告)号：US07180379B1
公开(公告)日：2007-02-20
申请号：US10838485
申请日：2004-05-03
IPC分类号： G01N21/00
CPC分类号： G06F1/105
摘要： A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.
摘要翻译： 通过将每个本地时钟电路中的光电导区域暴露于以固定频率工作的脉冲光源，同时在多个本地时钟电路中产生同步时钟信号。 光电导区产生足以导致逻辑逆变器切换状态的光电流。
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公开(公告)号：US07298653B1
公开(公告)日：2007-11-20
申请号：US10873872
申请日：2004-06-21
IPC分类号： G11C11/34
CPC分类号： G11C29/02 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.
摘要翻译： 在EEPROM阵列中，单元被预充电或预擦除，使得它们将均匀地响应于相同的读取电压电平。 通过明确定义其擦除状态和编程状态下的单元的阈值电压，可以定义多个读取电压，从而提供存储多个值和甚至模拟值的单元。
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5.发明授权Method and structure for addressing hot carrier degradation in high voltage devices 有权解决高压设备热载流子劣化的方法和结构公开(公告)号：US07180133B1
公开(公告)日：2007-02-20
申请号：US11016147
申请日：2004-12-17
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/0619 , H01L29/0634 , H01L29/086 , H01L29/0878 , H01L29/7835
摘要： In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.
摘要翻译： 在具有减少的热载流子劣化的高电压LDMOS的方法和结构中，消除了厚场氧化物，并且通过在漏极阱中包括相邻的p +和n +区域而将这些区域彼此短路，或者通过 包括漏极阱中的p +区，并将其偏压到相对于源极电压的正电压。
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公开(公告)号：US07050314B1
公开(公告)日：2006-05-23
申请号：US10625961
申请日：2003-07-23
IPC分类号： H02M3/18
CPC分类号： H02M3/07
摘要： A charge pump circuit in which at least one of the switching elements takes the form of a LVTSCR. The switching on and off of the LVTSCRs may be achieved by making use of a pulsed input and relying on the triggering and holding voltages of the LVTSCRs to switch on and off.
摘要翻译： 一种电荷泵电路，其中至少一个开关元件采取LVTSCR的形式。 LVTSCR的接通和断开可以通过使用脉冲输入并依靠LVTSCR的触发和保持电压来接通和关断来实现。
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7.发明申请公开(公告)号：US20070066002A1
公开(公告)日：2007-03-22
申请号：US11601485
申请日：2006-11-17
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L29/1083 , H01L29/66659 , H01L29/78
摘要： An implant is added at the interface between the source region of an MOS transistor and the well material to improve dynamic IR drop performance. The additional implant raises the underlying capacitance of the source region. This, in turn, provides for an increase in charge storage which, in turn, provides for an improved level of protection against dynamic IR drop.
摘要翻译： 在MOS晶体管的源极区域和阱材料之间的界面处添加植入物，以改善动态IR滴落性能。 额外的植入物提高了源区域的底层电容。 这又反过来提供了电荷存储的增加，这进而提供了防止动态IR降低的改进的防护等级。
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公开(公告)号：US07259411B1
公开(公告)日：2007-08-21
申请号：US10728132
申请日：2003-12-04
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823885 , H01L21/823487 , H01L29/0653 , H01L29/0657 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.
摘要翻译： 垂直MOS晶体管具有垂直堆叠的源极区域，沟道区域和漏极区域以及从漏极区域的顶表面延伸穿过漏极区域，沟道区域并且部分地延伸到源极区域的沟槽 。 垂直MOS晶体管还具有对沟槽进行排列的绝缘层，以及接触绝缘层以填充沟槽的导电栅极区域。
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公开(公告)号：US07221036B1
公开(公告)日：2007-05-22
申请号：US11129957
申请日：2005-05-16
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7322 , H01L27/0259 , H01L29/0821
摘要： A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
摘要翻译： 将一个压载区域放置在双极结晶体管的基极区域和集电极触点之间，以将热点移离晶体管的集电极触点。 将热点从集电极接触点移开可防止集电极接触在静电放电（ESD）脉冲期间熔化。
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公开(公告)号：US07075341B1
公开(公告)日：2006-07-11
申请号：US10823455
申请日：2004-04-13
IPC分类号： H03B1/00
CPC分类号： H01L27/0266
摘要： A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.
摘要翻译： 提供消耗片上低空间的线性时间驱动电路。 时间驱动电路基于5V容限级联NMOS器件，单栅极器件和齐纳二极管的合并区域的小电容器电荷。
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