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公开(公告)号：US07750835B1
公开(公告)日：2010-07-06
申请号：US12266299
申请日：2008-11-06
IPC分类号： H03M1/50
摘要： A digital to analog converter includes a time encoder that converts an analog input signal into a asynchronous pulse sequence, a pulse asynchronous DeMUX circuit that converts the asynchronous pulse sequence into a parallel stream of pulse sequences at a relatively lower speed, a parallel pulse to asynchronous digital converter, an asynchronous digital to synchronous digital converter, a timing reference circuit to generate absolute time references, and a Digital Signal Processor. This architecture provides for analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal.
摘要翻译： 数模转换器包括将模拟输入信号转换为异步脉冲序列的时间编码器，将异步脉冲序列转换成并行的脉冲序列流以相对较低速度的脉冲异步DeMUX电路， 数字转换器，异步数字到同步数字转换器，用于产生绝对时间基准的定时参考电路和数字信号处理器。 该架构提供了基于脉冲编码的模数转换，并具有脉冲编码信号的并行数字化方案。
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公开(公告)号：US07515084B1
公开(公告)日：2009-04-07
申请号：US11726484
申请日：2007-03-22
IPC分类号： H03M1/60
摘要： A digital to analog converter includes a time encoder that converts an analog input signal into a asynchronous pulse sequence, a pulse asynchronous DeMUX circuit that converts the asynchronous pulse sequence into a parallel stream of pulse sequences at a relatively lower speed, a parallel pulse to asynchronous digital converter, an asynchronous digital to synchronous digital converter, a timing reference circuit to generate absolute time references, and a Digital Signal Processor. This architecture provides for analog to digital conversion based on pulse encoding with a parallel digitization scheme of the pulse encoded signal.
摘要翻译： 数模转换器包括将模拟输入信号转换为异步脉冲序列的时间编码器，将异步脉冲序列转换成并行的脉冲序列流以相对较低速度的脉冲异步DeMUX电路， 数字转换器，异步数字到同步数字转换器，用于产生绝对时间基准的定时参考电路和数字信号处理器。 该架构提供了基于脉冲编码的模数转换，并具有脉冲编码信号的并行数字化方案。
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公开(公告)号：US07948869B2
公开(公告)日：2011-05-24
申请号：US11946844
申请日：2007-11-29
IPC分类号： H04J7/00
CPC分类号： H04B14/026
摘要： The present invention relates to a digital communication architecture based upon the concept of time encoding. In one aspect, systems provide time-encoding-based digital communication, the systems comprising a transmitter, a communication channel, and a receiver. In another aspect, methods for digital communication comprise time encoding digital input data and then transmitting the resultant asynchronous pulse signal to a receiver that converts the asynchronous pulse signal back into digital symbols. Methods of providing a digital communication link can include (i) providing digital symbols, (ii) time encoding the digital symbols to generate asynchronous pulse signals, (iii) communicating switching times of the signals to a receiver, and (iv) digitizing in parallel and reconstructing the digital symbols. The methods and systems of the invention can utilize existing chip-scale circuit technologies and can be characterized by link capacities of 50 Gbit/sec, 100 Gbit/sec, 200 Gbit/sec, or higher.
摘要翻译： 本发明涉及一种基于时间编码概念的数字通信体系结构。 在一个方面，系统提供基于时间编码的数字通信，所述系统包括发射机，通信信道和接收机。 在另一方面，用于数字通信的方法包括对数字输入数据进行时间编码，然后将合成的异步脉冲信号发送到将异步脉冲信号转换回数字符号的接收机。 提供数字通信链路的方法可以包括（i）提供数字符号，（ii）对数字符号进行时间编码以产生异步脉冲信号，（iii）将信号的切换时间传送到接收机，以及（iv）并行数字化 并重建数字符号。 本发明的方法和系统可以利用现有的芯片级电路技术，其特点可以是50Gbit / s，100Gbit / sec，200Gbit / sec或更高的链路容量。
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公开(公告)号：US20090141815A1
公开(公告)日：2009-06-04
申请号：US11946844
申请日：2007-11-29
IPC分类号： H04B14/04
CPC分类号： H04B14/026
摘要： The present invention relates to a digital communication architecture based upon the concept of time encoding. In one aspect, systems provide time-encoding-based digital communication, the systems comprising a transmitter, a communication channel, and a receiver. In another aspect, methods for digital communication comprise time encoding digital input data and then transmitting the resultant asynchronous pulse signal to a receiver that converts the asynchronous pulse signal back into digital symbols. Methods of providing a digital communication link can include (i) providing digital symbols, (ii) time encoding the digital symbols to generate asynchronous pulse signals, (iii) communicating switching times of the signals to a receiver, and (iv) digitizing in parallel and reconstructing the digital symbols. The methods and systems of the invention can utilize existing chip-scale circuit technologies and can be characterized by link capacities of 50 Gbit/sec, 100 Gbit/sec, 200 Gbit/sec, or higher.
摘要翻译： 本发明涉及一种基于时间编码概念的数字通信体系结构。 在一个方面，系统提供基于时间编码的数字通信，所述系统包括发射机，通信信道和接收机。 在另一方面，用于数字通信的方法包括对数字输入数据进行时间编码，然后将合成的异步脉冲信号发送到将异步脉冲信号转换回数字符号的接收机。 提供数字通信链路的方法可以包括（i）提供数字符号，（ii）对数字符号进行时间编码以产生异步脉冲信号，（iii）将信号的切换时间传送到接收机，以及（iv）并行数字化 并重建数字符号。 本发明的方法和系统可以利用现有的芯片级电路技术，其特点可以是50Gbit / s，100Gbit / sec，200Gbit / sec或更高的链路容量。
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5.发明授权Asynchronous pulse processing apparatus and method providing signal normalization 有权异步脉冲处理装置和方法提供信号归一化公开(公告)号：US08174425B1
公开(公告)日：2012-05-08
申请号：US12815350
申请日：2010-06-14
IPC分类号： H03M1/50
CPC分类号： H03K7/08
摘要： An asynchronous pulse processing (APP) apparatus, an APP system and a method of signal normalization employing APP provide signal normalization. The APP apparatus includes a gain block configured to scale an input signal by a first scale value and a summation block configured to produce a composite signal by subtracting from the scaled input signal each of a normalized signal scaled by a second scale value and the normalized signal multiplied by a summation signal. The APP apparatus further includes an integrator and a time encoder configured to produce the normalized signal from the composite signal. The APP system includes a plurality of APP apparatuses as APP channels. The method of signal normalization includes generating the composite signal from the scaled input signal and integrating and time encoding the composite signal to produce the normalized signal.
摘要翻译： 采用APP的异步脉冲处理（APP）装置，APP系统和信号归一化方法提供信号归一化。 APP装置包括：增益块，被配置为按照第一比例值缩放输入信号;以及求和块，其被配置为通过从缩放的输入信号中减去由第二比例值缩放的归一化信号和归一化信号 乘以求和信号。 APP装置还包括积分器和时间编码器，其被配置为从复合信号产生归一化信号。 APP系统包括作为APP通道的多个APP装置。 信号归一化的方法包括从缩放的输入信号产生复合信号，并对复合信号进行积分和时间编码以产生归一化信号。
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公开(公告)号：US07724168B1
公开(公告)日：2010-05-25
申请号：US12262782
申请日：2008-10-31
申请人： Jose Cruz-Albrecht , Peter Petre
发明人： Jose Cruz-Albrecht , Peter Petre
IPC分类号： H03M1/88
CPC分类号： G06G7/18
摘要： A system for making a pulse domain linear programming circuit. The inputs and the outputs to the pulse domain linear programming circuit are time encoded pulse signals. The circuit includes arrays of two types of cross-coupled time encoding elements. The first type of elements includes two integrators, adders, a hysteresis quantizer, and a 1-bit self-feedback DAC. The second type of elements includes a bias element, a leaky integrator, adders, a fixed memory-less non-linearity, a regular integrator, a hysteresis quantizer and a 1-bit self-feedback DAC. The cross-coupling signals between the two types of elements are pulse time-encoded signals. All of the cross-coupling weights are set via 1-bit DACs having variable gains. The cross-coupling weights are used to set a constraint equation of a pulse domain linear programming problem. Methods to make the foregoing circuit are also described.
摘要翻译： 一种用于制作脉冲域线性编程电路的系统。 脉冲域线性编程电路的输入和输出是时间编码脉冲信号。 该电路包括两种交叉耦合时间编码元件的阵列。 第一类元件包括两个积分器，加法器，滞后量化器和1位自反馈DAC。 第二类型的元件包括偏置元件，泄漏积分器，加法器，固定的无存储器非线性，常规积分器，滞后量化器和1位自反馈DAC。 两种类型的元件之间的交叉耦合信号是脉冲时间编码信号。 所有的交叉耦合权重通过具有可变增益的1位DAC来设置。 交叉耦合权重用于设置脉冲域线性规划问题的约束方程。 还描述了制作上述电路的方法。
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公开(公告)号：US08566265B1
公开(公告)日：2013-10-22
申请号：US13044922
申请日：2011-03-10
申请人： Jose Cruz-Albrecht , Peter Petre
发明人： Jose Cruz-Albrecht , Peter Petre
CPC分类号： G06N3/02 , G06N3/049 , G06N3/063 , H03M1/1023
摘要： A neural network has an array of interconnected processors, at least a first processor in the array operating in a pulse domain and at least a second processor in the array operating in a spike domain, and each said processor having: first inputs selectively coupled to other processors in the array of interconnected processors, each first input having an associated VCCS (a 1 bit DAC) coupled to a summing node, second inputs selectively coupled to inputs of the neural network, the second inputs having current generators associated therewith coupled to said summing node, a filter/integrator for generating an analog signal corresponding to current arriving at the summing node, and for processors operating in the pulse domain, an analog-to-pulse converter for converting an analog signal derived either directly from the filter/integrator or via a non-linear element, to the pulse domain, and providing the converted analog signal as an unquantized pulse domain signal at an output of each processor operating in the pulse domain and for processors operating in the spike domain, an analog-to-spike converter for converting an analog signal derived either directly from the filter/integrator or via a non-linear element, to the spike domain, and providing the converted analog signal as an unquantized spike domain signal at an output of each processor operating in the spike domain; wherein the array of interconnected processors are selectively interconnected with unquantized pulse domain and spike domain signals.
摘要翻译： 神经网络具有互连的处理器的阵列，阵列中的至少第一处理器以脉冲域操作，并且阵列中的至少第二处理器在尖峰域中操作，并且每个所述处理器具有：选择性地耦合到其它的第一输入 所述互连处理器阵列中的处理器，每个第一输入具有耦合到求和节点的相关联的VCCS（1比特DAC），所述第二输入选择性地耦合到所述神经网络的输入，所述第二输入具有与之相关联的电流发生器耦合到所述求和 节点，用于产生对应于到达求和节点的电流的模拟信号的滤波器/积分器，以及用于在脉冲域中操作的处理器的模拟 - 脉冲转换器，用于转换直接从滤波器/积分器导出的模拟信号或 通过非线性元件到脉冲域，并且在每次处理的输出处提供转换的模拟信号作为未量化的脉冲域信号 在脉冲域中操作的流水线以及在尖峰域中操作的处理器的模拟 - 尖峰转换器，用于将直接从滤波器/积分器或经由非线性元件导出的模拟信号转换为尖峰域，并提供 转换的模拟信号作为在尖峰域中操作的每个处理器的输出处的非量化尖峰域信号; 其中所述互连的处理器的阵列选择性地与未量化的脉冲域和尖峰域信号互连。
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公开(公告)号：US07996452B1
公开(公告)日：2011-08-09
申请号：US11595107
申请日：2006-11-10
申请人： Jose Cruz-Albrecht , Peter Petre
发明人： Jose Cruz-Albrecht , Peter Petre
CPC分类号： G06G7/161
摘要： A hadamard gate includes two strongly cross-coupled limit cycle oscillators. Each limit cycle oscillator includes an amplifier, a summing node, an integrator, a hysteresis quantizer, a self-feedback 1-bit DAC (Digital-to-Analog Converter) and a cross-feedback 1 bit DAC. Each oscillator output drives its own self-feedback DAC and the cross-feedback DAC of the other oscillator.
摘要翻译： 一个hadamard门包括两个强交叉耦合限位循环振荡器。 每个极限周期振荡器包括放大器，求和节点，积分器，滞后量化器，自反馈1位DAC（数模转换器）和交叉反馈1位DAC。 每个振荡器输出驱动其自身的反馈DAC和另一个振荡器的交叉反馈DAC。
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公开(公告)号：US20090141780A1
公开(公告)日：2009-06-04
申请号：US11946850
申请日：2007-11-29
申请人： Jose Cruz-Albrecht , Peter Petre
发明人： Jose Cruz-Albrecht , Peter Petre
CPC分类号： H04L25/03834 , H04L25/38 , H04L27/0014 , H04L2027/0024
摘要： The disclosed invention provides apparatus and methods that can convert frequencies of time-encoded signals. In one aspect, a down-converter circuit includes low-pass filters, a switch, a time encoder, and an output low-pass filter. In another aspect, an up-converter circuit includes an analog or digital input time encoder, low-pass filters, a switch, an output time encoder, and a time-encoded band-pass filter. In yet another aspect, a complete receiver system is provided. The receiver system can operate effectively with signals in the radio frequency range.
摘要翻译： 所公开的发明提供了可以转换时间编码信号的频率的装置和方法。 一方面，下变频电路包括低通滤波器，开关，时间编码器和输出低通滤波器。 在另一方面，上变换器电路包括模拟或数字输入时间编码器，低通滤波器，开关，输出时间编码器和时间编码带通滤波器。 在另一方面，提供了完整的接收机系统。 接收机系统可以在射频范围内的信号中有效地进行操作。
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公开(公告)号：US08659656B1
公开(公告)日：2014-02-25
申请号：US12902419
申请日：2010-10-12
申请人： Jose Cruz-Albrecht , Peter Petre
发明人： Jose Cruz-Albrecht , Peter Petre
CPC分类号： G06K9/00986 , G06K9/0063
摘要： Methods, circuits, and systems for time encoder-based unmixing of hyperspectral imaging data are disclosed. A method of unmixing hyperspectral imaging data includes receiving mixed image data of one or more pixels. The mixed image data is generated by an imaging device that captures hyperspectral data. The mixed image data includes sensed spectral band intensities of materials in an area represented by a particular pixel. The mixed image data is converted from first analog domain signals into pulse domain signals. A solution to a mixing equation in the pulse domain is generated to identify abundances of one or more of the materials based on the sensed spectral band intensities. The sensed spectral band intensities are compared to reference spectral band intensities of a set of considered materials. The solution is converted from a pulse domain into an analog domain as second analog domain signals.
摘要翻译： 公开了用于基于时间编码器的高光谱成像数据解混合的方法，电路和系统。 解混合高光谱成像数据的方法包括接收一个或多个像素的混合图像数据。 混合图像数据由捕获高光谱数据的成像装置产生。 混合图像数据包括由特定像素表示的区域中的材料的感测光谱带强度。 混合图像数据从第一模拟域信号转换成脉冲域信号。 产生脉冲域中的混合方程的解，以基于感测的光谱带强度来识别一种或多种材料的丰度。 将感测的光谱带强度与一组所考虑的材料的参考光谱带强度进行比较。 该解决方案从脉冲域转换为模拟域作为第二模拟域信号。
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