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    NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface
    1.
    发明授权
    NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
    基于NAND的混合NVM设计，在单模并行接口中集成NAND和NOR

    公开(公告)号：US08775719B2

    公开(公告)日：2014-07-08

    申请号：US12807996

    申请日：2010-09-17

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    IPC分类号： G06F12/00

    CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1075 ,  G11C2216/22

    摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

    摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在并行接口上传输。 并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

    Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface
    2.
    发明申请
    Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface 失效
    新型基于NAND的混合NVM设计，将NAND和NOR集成在1模并行接口中

    公开(公告)号：US20110072200A1

    公开(公告)日：2011-03-24

    申请号：US12807996

    申请日：2010-09-17

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    IPC分类号： G06F12/02 ,  G11C16/06

    CPC分类号： G11C16/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1075 ,  G11C2216/22

    摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A parallel interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the parallel interface at the rising edge and the falling edge of the synchronizing clock. The parallel interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

    摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 并行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在并行接口上传输。 并行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

    NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface
    3.
    发明授权
    NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 有权
    基于NAND的混合NVM设计，将NAND和NOR与1串口串行接口集成

    公开(公告)号：US08996785B2

    公开(公告)日：2015-03-31

    申请号：US12807997

    申请日：2010-09-17

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    IPC分类号： G06F12/00 ,  G11C16/32 ,  G11C16/04

    CPC分类号： G11C16/32 ,  G11C16/0408

    摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

    摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

    Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface
    4.
    发明申请
    Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 有权
    新型基于NAND的混合NVM设计，将NAND和NOR集成在1-die与串行接口中

    公开(公告)号：US20110072201A1

    公开(公告)日：2011-03-24

    申请号：US12807997

    申请日：2010-09-17

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    IPC分类号： G06F12/02 ,  G11C16/06

    CPC分类号： G11C16/32 ,  G11C16/0408

    摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. Reading one nonvolatile memory array may be interrupted for reading another. One reading operation has two sub-addresses with one transferred prior to a command.

    摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 读取一个非易失性存储器阵列可能会中断读取另一个。 一次读取操作具有两个子地址，一个命令之前传送一个。

    Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface
    5.
    发明申请
    Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface 审中-公开
    新型基于NAND的混合NVM设计，将NAND和NOR集成在1-die与串行接口中

    公开(公告)号：US20110051519A1

    公开(公告)日：2011-03-03

    申请号：US12807080

    申请日：2010-08-27

    申请人： Peter W. Lee ,  Kesheng Wang ,  Fu-Chang Hsu

    发明人： Peter W. Lee ,  Kesheng Wang ,  Fu-Chang Hsu

    IPC分类号： G11C16/04

    CPC分类号： G11C16/32 ,  G11C7/1075

    摘要： A nonvolatile memory device includes multiple independent nonvolatile memory arrays that concurrently for parallel reading and writing the nonvolatile memory arrays. A serial interface communicates commands, address, device status, and data between a master device and nonvolatile memory arrays for concurrently reading and writing of the nonvolatile memory arrays and sub-arrays. Data is transferred on the serial interface at the rising edge and the falling edge of the synchronizing clock. The serial interface transmits a command code and an address code from a master device and transfers a data code between the master device and the nonvolatile memory device, wherein the data code has a length that is determined by the command code and a location determined by the address code. An enable signal defines a beginning and termination of a reading or writing operation. Reading one nonvolatile memory array may be interrupted for another operation and then resumed.

    摘要翻译： 非易失性存储器件包括多个独立的非易失性存储器阵列，用于并行读写非易失性存储器阵列。 串行接口在主设备和非易失性存储器阵列之间传送命令，地址，设备状态和数据，用于同时读写非易失性存储器阵列和子阵列。 数据在同步时钟的上升沿和下降沿在串行接口上​​传输。 串行接口从主设备发送命令代码和地址代码，并在主设备和非易失性存储设备之间传送数据代码，其中数据代码具有由命令代码确定的长度和由 地址代码 启用信号定义读取或写入操作的开始和结束。 读取一个非易失性存储器阵列可能被中断用于另一个操作，然后恢复。

    MEMORY SYSTEM HAVING NAND-BASED NOR AND NAND FLASHES AND SRAM INTEGRATED IN ONE CHIP FOR HYBRID DATA, CODE AND CACHE STORAGE
    6.
    发明申请
    MEMORY SYSTEM HAVING NAND-BASED NOR AND NAND FLASHES AND SRAM INTEGRATED IN ONE CHIP FOR HYBRID DATA, CODE AND CACHE STORAGE 失效
    具有基于NAND的NAND和NAND闪存的存储器系统和集成在一个芯片中的SRAM用于混合数据，代码和缓存存储

    公开(公告)号：US20100329011A1

    公开(公告)日：2010-12-30

    申请号：US12701509

    申请日：2010-02-05

    申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    IPC分类号： G11C16/04

    CPC分类号： G11C16/04 ,  G11C7/1075 ,  G11C8/16

    摘要： A memory system includes a NAND flash memory, a NOR flash memory and a SRAM manufactured on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.

    摘要翻译： 存储器系统包括NAND闪存，NOR闪存和在单个芯片上制造的SRAM。 NAND和NOR存储器都由相同的NAND制造工艺和NAND单元制造。 三个存储器共享相同的地址总线，数据总线和单个芯片的引脚。 地址总线是双向的，用于接收代码，数据和地址以及发送输出。 数据总线也是双向的，用于接收和发送数据。 一个外部芯片使能引脚和一个外部输出使能引脚由三个存储器共享，以减少单个芯片所需的引脚数。 NAND和NOR存储器都具有双读取页面缓冲器和用于Read-While-Load和Write-While-Program-Write操作的双写入页面缓冲器，以分别加速读取和写入操作。 存储器映射方法用于选择不同的存储器，状态寄存器和双读或写页缓冲器。

    Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage
    7.
    发明授权
    Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage 失效
    具有基于NAND的NOR和NAND闪存的存储器系统和集成在一个芯片中的SRAM用于混合数据，代码和高速缓存存储

    公开(公告)号：US08149622B2

    公开(公告)日：2012-04-03

    申请号：US12701509

    申请日：2010-02-05

    申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Kesheng Wang

    IPC分类号： G11C16/04

    CPC分类号： G11C16/04 ,  G11C7/1075 ,  G11C8/16

    摘要： A memory system includes a NAND flash memory, a NOR flash memory and a SRAM memory on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.

    摘要翻译： 存储器系统包括NAND闪存，NOR闪存和单个芯片上的SRAM存储器。 NAND和NOR存储器都由相同的NAND制造工艺和NAND单元制造。 三个存储器共享相同的地址总线，数据总线和单个芯片的引脚。 地址总线是双向的，用于接收代码，数据和地址以及发送输出。 数据总线也是双向的，用于接收和发送数据。 一个外部芯片使能引脚和一个外部输出使能引脚由三个存储器共享，以减少单个芯片所需的引脚数。 NAND和NOR存储器都具有双读取页面缓冲器和用于Read-While-Load和Write-While-Program-Write操作的双写入页面缓冲器，以分别加速读取和写入操作。 存储器映射方法用于选择不同的存储器，状态寄存器和双读或写页缓冲器。

    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
    8.
    发明授权
    Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout 有权
    单片，组合非易失性存储器允许字节，页和块写入，无扰动和分割，在单元阵列中使用统一的单元结构和技术与解码器和布局的新方案

    公开(公告)号：US07372736B2

    公开(公告)日：2008-05-13

    申请号：US11391662

    申请日：2006-03-28

    申请人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    发明人： Peter W. Lee ,  Fu-Chang Hsu ,  Hsing-Ya Tsao ,  Han-Rei Ma

    IPC分类号： G11C16/04 ,  H01L29/76 ,  H01L23/544

    CPC分类号： H01L27/11521 ,  G11C16/0408 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/14 ,  H01L27/115 ,  H01L27/11524

    摘要： A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim tunneling at relatively high voltages.

    摘要翻译： 非易失性存储器阵列具有单个晶体管闪存单元和可集成在同一衬底上的两个晶体管EEPROM存储单元。 非易失性存储单元具有低耦合系数的浮动栅极，以允许更小的存储单元。 浮置栅极放置在隧道绝缘层之上，浮动栅极与源极区域和漏极区域的边缘对准，并且具有由源极漏极的边缘的宽度限定的宽度。 浮动栅极和控制栅极具有小于50％的相对小的耦合比，以允许非易失性存储单元的缩放。 非易失性存储单元用通道热电子编程进行编程，并以相对高的电压用Fowler Nordheim隧道擦除。