公开(公告)号：US20100329011A1

公开(公告)日：2010-12-30

申请号：US12701509

申请日：2010-02-05

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C7/1075 ,  G11C8/16

摘要： A memory system includes a NAND flash memory, a NOR flash memory and a SRAM manufactured on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.

摘要翻译： 存储器系统包括NAND闪存，NOR闪存和在单个芯片上制造的SRAM。 NAND和NOR存储器都由相同的NAND制造工艺和NAND单元制造。 三个存储器共享相同的地址总线，数据总线和单个芯片的引脚。 地址总线是双向的，用于接收代码，数据和地址以及发送输出。 数据总线也是双向的，用于接收和发送数据。 一个外部芯片使能引脚和一个外部输出使能引脚由三个存储器共享，以减少单个芯片所需的引脚数。 NAND和NOR存储器都具有双读取页面缓冲器和用于Read-While-Load和Write-While-Program-Write操作的双写入页面缓冲器，以分别加速读取和写入操作。 存储器映射方法用于选择不同的存储器，状态寄存器和双读或写页缓冲器。

公开(公告)号：US08149622B2

公开(公告)日：2012-04-03

申请号：US12701509

申请日：2010-02-05

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Kesheng Wang

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Kesheng Wang

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C7/1075 ,  G11C8/16

摘要： A memory system includes a NAND flash memory, a NOR flash memory and a SRAM memory on a single chip. Both NAND and NOR memories are manufactured by the same NAND manufacturing process and NAND cells. The three memories share the same address bus, data bus, and pins of the single chip. The address bus is bi-directional for receiving codes, data and addresses and transmitting output. The data bus is also bi-directional for receiving and transmitting data. One external chip enable pin and one external output enable pin are shared by the three memories to reduce the number of pins required for the single chip. Both NAND and NOR memories have dual read page buffers and dual write page buffers for Read-While-Load and Write-While-Program operations to accelerate the read and write operations respectively. A memory-mapped method is used to select different memories, status registers and dual read or write page buffers.

摘要翻译： 存储器系统包括NAND闪存，NOR闪存和单个芯片上的SRAM存储器。 NAND和NOR存储器都由相同的NAND制造工艺和NAND单元制造。 三个存储器共享相同的地址总线，数据总线和单个芯片的引脚。 地址总线是双向的，用于接收代码，数据和地址以及发送输出。 数据总线也是双向的，用于接收和发送数据。 一个外部芯片使能引脚和一个外部输出使能引脚由三个存储器共享，以减少单个芯片所需的引脚数。 NAND和NOR存储器都具有双读取页面缓冲器和用于Read-While-Load和Write-While-Program-Write操作的双写入页面缓冲器，以分别加速读取和写入操作。 存储器映射方法用于选择不同的存储器，状态寄存器和双读或写页缓冲器。

公开(公告)号：US08634254B2

公开(公告)日：2014-01-21

申请号：US13052049

申请日：2011-03-19

申请人： Fu-Chang Hsu ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Peter Wung Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/06

摘要： A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a first plate connected to a floating gate of the storage MOS transistor to form a floating gate node. The coupling PIP or MIM capacitor couples the voltage level applied to a second plate of the PIP or MIM capacitor to the floating gate node with a large coupling ratio approximately 90% so as to initiate Fowler-Nordheim tunneling effect for erasing or programming the memory device. The memory device may also have another PIP or MIM capacitor with a first plate connected to the floating gate of the storage MOS transistor for serving as a tunneling capacitor.

摘要翻译： 单个多晶硅浮栅非易失性存储器件具有存储MOS晶体管和至少一个多晶绝缘体 - 多晶（PIP）或金属 - 绝缘体 - 金属（MIM）电容器，其制造尺寸可以使用当前的低电压逻辑集成电路 处理。 PIP或MIM电容器是耦合电容器，其中第一板连接到存储MOS晶体管的浮置栅极，以形成浮动栅极节点。 耦合PIP或MIM电容将施加到PIP或MIM电容器的第二板的电压电平耦合到具有大约90％的大耦合比的浮动栅极节点，以便启动用于擦除或编程存储器件的Fowler-Nordheim隧道效应 。 存储器件还可以具有另一个PIP或MIM电容器，其中第一板连接到用作隧道电容器的存储MOS晶体管的浮置栅极。

公开(公告)号：US08531885B2

公开(公告)日：2013-09-10

申请号：US13116002

申请日：2011-05-26

申请人： Fu-Chang Hsu ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Peter Wung Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/0433 ,  G11C16/0483 ,  H01L27/1021 ,  H01L27/11524 ,  H01L29/872

摘要： A NAND-based NOR flash memory array has a matrix of NAND-based NOR flash cells arranged in rows and columns. Every two adjacent NAND-based NOR flash cells in a column share a common source node which is connected to a common source line through a diode. The source line may be made of a metal layer and is in contact directly with the source node or through an ohmic contact to form a Schottky barrier diode. The source line may also be made of a polysilicon or metal layer and connected to the source node through a pillar-structured polysilicon diode and a conduction layer. The diode may also be formed in the source node by enclosing a P/N+ junction diode in a heavily N+ doped region of the source node.

摘要翻译： 基于NAND的NOR闪存阵列具有以行和列排列的基于NAND的NOR闪存单元的矩阵。 列中每两个相邻的基于NAND的NOR闪存单元共享通过二极管连接到公共源极线的公共源节点。 源极线可以由金属层制成并且与源节点直接接触或通过欧姆接触形成肖特基势垒二极管。 源极线还可以由多晶硅或金属层制成并且通过柱结构的多晶硅二极管和导电层连接到源节点。 二极管也可以通过在源节点的重N +掺杂区域中封装P / N +结二极管而形成在源节点中。

公开(公告)号：US08472251B2

公开(公告)日：2013-06-25

申请号：US12378036

申请日：2009-02-10

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/04 ,  G11C11/34 ,  H01L29/788 ,  H01L29/66

CPC分类号： H01L29/7883 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/11558 ,  H01L29/42324

摘要： A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (greater than 80%) between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.

摘要翻译： 单个多晶硅浮动非易失性存储单元具有MOS电容器和存储MOS晶体管，其制造尺寸允许使用电流低电压逻辑集成电路工艺制造。 MOS电容器具有连接到存储MOS晶体管的栅极的第一板，以形成浮栅节点。 与存储MOS晶体管的物理尺寸相比，MOS电容器的物理尺寸相对较大（大约10倍），以在MOS电容器的第二板和浮置电容器之间建立大的耦合比（大于80％） 门节点。 当向MOS电容器的第二板施加电压，并且施加到MOS晶体管的源极区域或漏极区域的电压在MOS晶体管的栅极氧化物内建立电压场，从而启动Fowler-Nordheim边缘隧道。

公开(公告)号：US20120063233A1

公开(公告)日：2012-03-15

申请号：US13200010

申请日：2011-09-15

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/10 ,  H01L21/336

CPC分类号： H01L21/28273 ,  G11C16/0441 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7883

摘要： A nonvolatile memory device has a combination of FLOTOX EEPROM nonvolatile memory arrays. Each FLOTOX-based nonvolatile memory array is formed of FLOTOX-based nonvolatile memory cells that include at least one floating gate tunneling oxide transistor such that a coupling ratio of the control gate to the floating gate of the floating gate tunneling oxide transistor is from approximately 60% to approximately 70% and a coupling ratio of the floating gate to the drain region of the floating gate tunneling oxide transistor is maintained as a constant of is from approximately 10% to approximately 20% and such that a channel length of the channel region is decreased such that during the programming procedure a negative programming voltage level is applied to the control gate and a moderate positive programming voltage level is applied to the drain region to prevent the moderate positive programming voltage level from exceeding a drain-to-source breakdown voltage.

公开(公告)号：US20110235437A1

公开(公告)日：2011-09-29

申请号：US13052049

申请日：2011-03-19

申请人： Fu-Chang Hsu ,  Peter Wung Lee

发明人： Fu-Chang Hsu ,  Peter Wung Lee

IPC分类号： G11C16/14 ,  G11C16/02

CPC分类号： G11C16/0466 ,  G11C16/06

摘要： A single polycrystalline silicon floating gate nonvolatile memory device has a storage MOS transistor and at least one polycrystalline-insulator-polycrystalline (PIP) or metal-insulator-metal (MIM) capacitor manufactured with dimensions that can be fabricated using current low voltage logic integrated circuit process. The PIP or MIM capacitor is a coupling capacitor with a first plate connected to a floating gate of the storage MOS transistor to form a floating gate node. The coupling PIP or MIM capacitor couples the voltage level applied to a second plate of the PIP or MIM capacitor to the floating gate node with a large coupling ratio approximately 90% so as to initiate Fowler-Nordheim tunneling effect for erasing or programming the memory device. The memory device may also have another PIP or MIM capacitor with a first pate connected to the floating gate of the storage MOS transistor for serving as a tunneling capacitor.

摘要翻译： 单个多晶硅浮栅非易失性存储器件具有存储MOS晶体管和至少一个多晶绝缘体 - 多晶（PIP）或金属 - 绝缘体 - 金属（MIM）电容器，其制造尺寸可以使用当前的低电压逻辑集成电路 处理。 PIP或MIM电容器是耦合电容器，其中第一板连接到存储MOS晶体管的浮置栅极，以形成浮动栅极节点。 耦合PIP或MIM电容将施加到PIP或MIM电容器的第二板的电压电平耦合到具有大约90％的大耦合比的浮动栅极节点，以便启动用于擦除或编程存储器件的Fowler-Nordheim隧道效应 。 存储器件还可以具有另一个PIP或MIM电容器，其中第一头连接到存储MOS晶体管的浮置栅极用作隧道电容器。

公开(公告)号：US20090201742A1

公开(公告)日：2009-08-13

申请号：US12378036

申请日：2009-02-10

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/06 ,  H01L29/788 ,  H01L29/94

CPC分类号： H01L29/7883 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/11558 ,  H01L29/42324

摘要： A single polycrystalline silicon floating gate nonvolatile memory cell has a MOS capacitor and a storage MOS transistor fabricated with dimensions that allow fabrication using current low voltage logic integrated circuit process. The MOS capacitor has a first plate connected to a gate of the storage MOS transistor to form a floating gate node. The physical size of the MOS capacitor is relatively large (approximately 10 time greater) when compared to a physical size of the storage MOS transistor to establish a large coupling ratio (approximately 90% between the second plate of the MOS capacitor and the floating gate node. When a voltage is applied to the second plate of the MOS capacitor and a voltage applied to the source region or drain region of the MOS transistor establishes a voltage field within the gate oxide of the MOS transistor such that Fowler-Nordheim edge tunnel is initiated.

摘要翻译： 单个多晶硅浮动非易失性存储单元具有MOS电容器和存储MOS晶体管，其制造尺寸允许使用电流低电压逻辑集成电路工艺制造。 MOS电容器具有连接到存储MOS晶体管的栅极的第一板，以形成浮栅节点。 与存储MOS晶体管的物理尺寸相比，MOS电容器的物理尺寸相对较大（大约10倍），以建立大的耦合比（MOS电容器的第二板和浮动栅极节点之间的约90％ 当向MOS电容器的第二板施加电压并且施加到MOS晶体管的源极区域或漏极区域的电压在MOS晶体管的栅极氧化物内建立电压场，从而启动Fowler-Nordheim边缘隧道 。

公开(公告)号：US20080253186A1

公开(公告)日：2008-10-16

申请号：US12080894

申请日：2008-04-07

申请人： Peter Wung Lee ,  Fu-Chang Hsu

发明人： Peter Wung Lee ,  Fu-Chang Hsu

IPC分类号： G11C16/04 ,  H01L21/336 ,  G11C16/06

CPC分类号： G11C16/24 ,  G11C11/5671 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7923

摘要： A nonvolatile memory array includes a plurality of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells arranged in rows and columns. The dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells on each column form at least one grouping that is arranged in a NAND series string of dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells. Each NAND series string has a top select transistor and a bottom select transistor. Pairs of braided bit lines are connected in a braided columnar bit line structure such that each column of the dual-sided charge-trapping dual-sided charge-trapping nonvolatile memory cells is connected to an associated pair of braided bit lines.

摘要翻译： 非易失性存储器阵列包括以行和列布置的多个双面电荷俘获双面电荷捕获非易失性存储器单元。 每列上的双面电荷俘获双面电荷俘获非易失性存储器单元形成至少一个分组，其被布置在双面电荷俘获双面电荷俘获非易失性存储器单元的NAND串联串中。 每个NAND串联串具有顶部选择晶体管和底部选择晶体管。 编织的位线对被连接在编织的柱状位线结构中，使得双面电荷俘获双面电荷俘获非易失性存储器单元的每列连接到相关的一对编织位线。

公开(公告)号：US06166961A

公开(公告)日：2000-12-26

申请号：US377545

申请日：1999-08-19

申请人： Peter Wung Lee ,  Fu-Chang Hsu ,  Mike Hsinyih Chen

发明人： Peter Wung Lee ,  Fu-Chang Hsu ,  Mike Hsinyih Chen

IPC分类号： G11C5/14 ,  G11C16/10 ,  G11C16/16 ,  G11C16/04

CPC分类号： G11C16/102 ,  G11C5/145 ,  G11C16/16

摘要： In this invention external high voltages are connected to a chip containing a flash memory that are connected to selected cells to be erased. Internal pump circuits contained on the chip are turned off while the external voltages are used. The external voltages, a high negative voltage and a high positive voltage, are connected to gates and sources respectively of selected cells to be erased by a voltage control module. The external voltages are used during manufacture during program/erase operations to perform the erase function efficiently. The internal high voltage pump circuits are used to erase flash memory cells after being assembled on a circuit board by a user. Two level shifter circuits are disclosed that form a part of the voltage control module. The level shifter circuits apply voltages to the flash memory cells and provide voltages that select and deselect the cells for erasure.

摘要翻译： 在本发明中，外部高电压连接到包含连接到要擦除的所选单元的闪速存储器的芯片。 使用外部电压时，芯片上包含的内部泵电路关闭。 外部电压，高负电压和高正电压分别连接到要由电压控制模块擦除的所选单元的门和源。 在编程/擦除操作期间在制造期间使用外部电压以有效地执行擦除功能。 内部高压泵电路用于在由用户组装在电路板上之后擦除闪存单元。 公开了形成电压控制模块的一部分的两个电平移位器电路。 电平移位器电路向闪存单元施加电压并提供选择和取消选择单元用于擦除的电压。