公开(公告)号：US07400182B2

公开(公告)日：2008-07-15

申请号：US10915746

申请日：2004-08-11

申请人： Phil-Jae Jeon

发明人： Phil-Jae Jeon

IPC分类号： H03L7/06

CPC分类号： H03L7/081 ,  H03L7/0891 ,  H03L7/0996 ,  H03L7/0998 ,  H03L7/18

摘要： A clock generator based on a phase-locked loop with one pole and an improved period jitter characteristic is disclosed. The clock generator comprises a phase detector for generating a phase detection signal and a phase error signal, a charge pump for generating a loop control voltage, a loop filter for generating an integrated voltage signal, a voltage-controlled oscillator for generating multi-phase output signals, and a phase error compensating circuit for compensating a phase error generated at a prior input clock. The clock generator has an improved period jitter characteristic by compensating a phase error generated at a prior input clock.

摘要翻译： 公开了一种基于具有一极的锁相环和改进的周期抖动特性的时钟发生器。 时钟发生器包括用于产生相位检测信号和相位误差信号的相位检测器，用于产生环路控制电压的电荷泵，用于产生积分电压信号的环路滤波器，用于产生多相输出的压控振荡器 信号，以及用于补偿在先前输入时钟产生的相位误差的相位误差补偿电路。 通过补偿在先前输入时钟产生的相位误差，时钟发生器具有改善的周期抖动特性。

公开(公告)号：US06703902B2

公开(公告)日：2004-03-09

申请号：US10253072

申请日：2002-09-24

申请人： Phil-Jae Jeon ,  Myoung-su Lee

发明人： Phil-Jae Jeon ,  Myoung-su Lee

IPC分类号： H03L708

CPC分类号： H03C3/0975 ,  H03C3/0958 ,  H03L7/0996 ,  H03L7/0998 ,  H03L7/18

摘要： A phase locked loop (PLL) for reducing electromagnetic interference (EMI) is provided. The PLL is not sensitive to a manufacturing process, consumes less power, occupies a small layout space, and can flexibly control a modulation frequency and a modulation rate flexibly. The PLL for reducing the EMI controls the signals having a phase difference, which is n-times (where n is an integer) the basic delay time of the output signals from a voltage controlled oscillator (VCO), and determines the modulation rate. Then, the PLL repeats the procedure during the cycle of a pre-defined modulation frequency. The PLL for reducing the EMI not only reduces the EMI, but also does not require a ROM. Therefore, the layout space can be reduced and broad frequency ranges can be obtained. In addition, since the phase difference of the output signals of the VCO is controlled by logic circuits, the PLL is insensitive to changes in the manufacturing process.

摘要翻译： 提供了用于降低电磁干扰（EMI）的锁相环（PLL）。 PLL对制造过程不敏感，功耗较小，布局空间小，灵活控制调制频率和调制速率。 用于降低EMI的PLL控制具有来自压控振荡器（VCO）的输出信号的基本延迟时间的n倍（其中n是整数）的相位差的信号，并且确定调制率。 然后，PLL在预定义的调制频率的周期中重复该过程。 用于降低EMI的PLL不仅降低了EMI，而且不需要ROM。 因此，可以减小布局空间并且可以获得宽的频率范围。 此外，由于VCO的输出信号的相位差由逻辑电路控制，所以PLL对制造过程的变化不敏感。

公开(公告)号：US08036333B2

公开(公告)日：2011-10-11

申请号：US11846715

申请日：2007-08-29

申请人： Phil-Jae Jeon

发明人： Phil-Jae Jeon

IPC分类号： H03D3/24

CPC分类号： H04L7/10 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/18 ,  H04L7/033

摘要： A clock and data recovery circuit that does not use a reference clock and a method of recovering cocks and data, in which the clock and data recovery circuit includes a clock generation unit, a mirror delay unit, a preamble phase detection unit, and a sampling unit. The clock generation unit generates a clock signal such that a phase of the clock signal is locked to a phase of a data signal inputted to the clock generation unit. The mirror delay unit outputs a plurality of delayed preamble signals based on the preamble signal during a preamble period. The preamble phase detection unit provides the charge pump with a preamble phase detection signal having information on a phase difference between the preamble signal and the clock signal during the preamble period. The sampling unit extracts data from the data signal by sampling the data signal with the clock signal.

摘要翻译： 不使用参考时钟的时钟和数据恢复电路以及恢复电路和数据的方法，其中时钟和数据恢复电路包括时钟产生单元，镜像延迟单元，前导码相位检测单元和采样 单元。 时钟生成单元生成时钟信号，使得时钟信号的相位被锁定到输入到时钟生成单元的数据信号的相位。 镜像延迟单元在前导码周期期间基于前导信号输出多个延迟前导信号。 前导码相位检测单元在前导码周期期间为电荷泵提供具有关于前导信号和时钟信号之间的相位差的信息的前导码相位检测信号。 采样单元通过采用时钟信号对数据信号进行采样从数据信号中提取数据。

公开(公告)号：US20070035337A1

公开(公告)日：2007-02-15

申请号：US11495277

申请日：2006-07-28

申请人： Doh-Young Kim ,  Phil-Jae Jeon

发明人： Doh-Young Kim ,  Phil-Jae Jeon

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/095

摘要： A lock detector of a delay-locked loop (DLL) includes a lock detection unit and a bias unit. The lock detection unit generates a charge control signal based on a reference current received from an external source and a plurality of delay signals received from an external voltage-controlled delay line (VCDL), controls a charge current based on the charge control signal, and detects a lock state of the DLL based on a voltage that varies depending on the charge current. The bias unit provides a bias voltage for controlling a magnitude of the charge current. Therefore, the lock detector stably detects a lock state of the DLL.

摘要翻译： 延迟锁定环（DLL）的锁定检测器包括锁定检测单元和偏置单元。 锁定检测单元基于从外部源接收的参考电流和从外部电压控制延迟线（VCDL）接收的多个延迟信号产生充电控制信号，基于充电控制信号控制充电电流，以及 基于根据充电电流而变化的电压来检测DLL的锁定状态。 偏置单元提供用于控制充电电流的大小的偏置电压。 因此，锁定检测器稳定地检测DLL的锁定状态。

公开(公告)号：US07508245B2

公开(公告)日：2009-03-24

申请号：US11495277

申请日：2006-07-28

申请人： Doh-Young Kim ,  Phil-Jae Jeon

发明人： Doh-Young Kim ,  Phil-Jae Jeon

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/095

摘要： A lock detector of a delay-locked loop (DLL) includes a lock detection unit and a bias unit. The lock detection unit generates a charge control signal based on a reference current received from an external source and a plurality of delay signals received from an external voltage-controlled delay line (VCDL), controls a charge current based on the charge control signal, and detects a lock state of the DLL based on a voltage that varies depending on the charge current. The bias unit provides a bias voltage for controlling a magnitude of the charge current. Therefore, the lock detector stably detects a lock state of the DLL.

摘要翻译： 延迟锁定环（DLL）的锁定检测器包括锁定检测单元和偏置单元。 锁定检测单元基于从外部源接收的参考电流和从外部电压控制延迟线（VCDL）接收的多个延迟信号产生充电控制信号，基于充电控制信号控制充电电流，以及 基于根据充电电流而变化的电压来检测DLL的锁定状态。 偏置单元提供用于控制充电电流的大小的偏置电压。 因此，锁定检测器稳定地检测DLL的锁定状态。

公开(公告)号：US20050073343A1

公开(公告)日：2005-04-07

申请号：US10960367

申请日：2004-10-06

申请人： Woo-Seok Kim ,  Phil-Jae Jeon

发明人： Woo-Seok Kim ,  Phil-Jae Jeon

IPC分类号： H03L7/08 ,  H03L7/00 ,  H03L7/089 ,  H03L7/095

CPC分类号： H03L7/095 ,  H03L7/0891

摘要： A phase-locked loop circuit including a lock detection function is disclosed. The phase-locked loop circuit comprises a lock detection circuit. The lock detection circuit includes a lock-detection-start-signal generator, a lock-detection-clock generator, and a lock-detection-signal generator. The lock-detection-start-signal generates a lock detection start signal when the pulse width of an up signal and a down signal reaches a predetermined value. The lock-detection-clock generator generates a lock detection clock signal on the basis of the up signal and the down signal. The lock-detection-signal generator counts the lock detection clock signal, and generates the lock detection signal. The phase-locked loop circuit is capable of discriminating the operating regions thereof and outputting a lock detection signal when the locking of phase is completed.

摘要翻译： 公开了一种包括锁定检测功能的锁相环电路。 锁相环电路包括锁定检测电路。 锁定检测电路包括锁定检测启动信号发生器，锁定检测时钟发生器和锁定检测信号发生器。 当上升信号和下降信号的脉冲宽度达到预定值时，锁定检测启动信号产生锁定检测开始信号。 锁定检测时钟发生器基于上行信号和下降信号产生锁定检测时钟信号。 锁定检测信号发生器对锁定检测时钟信号进行计数，并产生锁定检测信号。 当相位锁定完成时，锁相环电路能够识别其工作区域并输出锁定检测信号。

公开(公告)号：US20080150597A1

公开(公告)日：2008-06-26

申请号：US11962429

申请日：2007-12-21

申请人： Wei Hu ,  Phil-Jae Jeon

发明人： Wei Hu ,  Phil-Jae Jeon

IPC分类号： H03L7/06

CPC分类号： H03L7/0995 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/0891

摘要： An apparatus for controlling a delay includes a phase locked loop and a delay unit. The phase locked loop generates an oscillation signal having a frequency substantially identical to that of a reference signal. The delay unit includes a delay cell block that outputs delayed signals by delaying the reference signal sequentially by a uniform delay interval. The delay unit controls the delay interval based on a frequency/phase difference between a first input signal and a second input signal of the phase locked loop, and outputs one of the delayed signals as a delayed reference signal. Related methods are also described.

摘要翻译： 用于控制延迟的装置包括锁相环和延迟单元。 锁相环产生具有与参考信号基本相同的频率的振荡信号。 延迟单元包括延迟单元块，其通过以均匀延迟间隔顺序延迟参考信号来输出延迟信号。 延迟单元基于第一输入信号和锁相环路的第二输入信号之间的频率/相位差来控制延迟间隔，并且将延迟信号之一作为延迟参考信号输出。 还描述了相关方法。

公开(公告)号：US20070081618A1

公开(公告)日：2007-04-12

申请号：US11523936

申请日：2006-09-20

申请人： Phil-Jae Jeon

发明人： Phil-Jae Jeon

IPC分类号： H04L7/02 ,  H03D3/24

CPC分类号： H03L7/0891 ,  H03L7/087 ,  H04L7/0004 ,  H04L7/033

摘要： An apparatus for recovering a clock and data includes a transition detecting circuit and a clock recovery circuit. The transition detecting circuit detects a transition of an input data signal to provide a transition interval of the input data signal. The clock recovery circuit generates a recovered clock based on the input data signal during the transition interval of the input data signal.

摘要翻译： 用于恢复时钟和数据的装置包括转换检测电路和时钟恢复电路。 转换检测电路检测输入数据信号的转变以提供输入数据信号的转换间隔。 时钟恢复电路在输入数据信号的转换间隔期间基于输入数据信号产生恢复的时钟。

公开(公告)号：US20050093598A1

公开(公告)日：2005-05-05

申请号：US10965450

申请日：2004-10-14

申请人： Phil-Jae Jeon ,  Doh-Young Kim

发明人： Phil-Jae Jeon ,  Doh-Young Kim

IPC分类号： G06F1/10 ,  H03K5/14 ,  H03K5/26 ,  H03L7/00 ,  H03L7/06 ,  H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/095 ,  H03L7/10

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/10

摘要： A delay-locked loop circuit includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled delay line and a coarse lock detector. The phase frequency detector generates an up signal and a down signal corresponding to phase and frequency differences between an input clock signal and a feedback signal. The charge pump receives the up signal, the down signal and a coarse lock detection signal to generate a current signal. The loop filter receives and filters the current signal through a low-pass filter to generate a direct voltage signal. The voltage controlled delay line receives the input clock signal and the direct voltage signal to generate the feedback signal and control signals. The coarse lock detector receives the control signals to generate the initialization signal and the coarse lock detection signal to adjust Td within Tin/2

摘要翻译： 延迟锁定环路包括相位频率检测器，电荷泵，环路滤波器，电压控制延迟线和粗略锁定检测器。 相位频率检测器产生对应于输入时钟信号和反馈信号之间的相位和频率差的上升信号和下降信号。 电荷泵接收上升信号，下降信号和粗略锁定检测信号以产生电流信号。 环路滤波器通过低通滤波器接收和滤波电流信号，以产生直流电压信号。 电压控制延迟线接收输入时钟信号和直流电压信号，以产生反馈信号和控制信号。 当Td> = 2xTin或Td <= Tin / 2时，粗锁检测器接收控制信号以产生初始化信号和粗锁检测信号，以调整Tin / 2

公开(公告)号：US20080056423A1

公开(公告)日：2008-03-06

申请号：US11846715

申请日：2007-08-29

申请人： Phil-Jae Jeon

发明人： Phil-Jae Jeon

IPC分类号： H04L7/02

CPC分类号： H04L7/10 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/18 ,  H04L7/033

摘要： A clock and data recovery circuit that does not use a reference clock and a method of recovering cocks and data, in which the clock and data recovery circuit includes a clock generation unit, a mirror delay unit, a preamble phase detection unit, and a sampling unit. The clock generation unit generates a clock signal such that a phase of the clock signal is locked to a phase of a data signal inputted to the clock generation unit. The mirror delay unit outputs a plurality of delayed preamble signals based on the preamble signal during a preamble period. The preamble phase detection unit provides the charge pump with a preamble phase detection signal having information on a phase difference between the preamble signal and the clock signal during the preamble period. The sampling unit extracts data from the data signal by sampling the data signal with the clock signal.

摘要翻译： 不使用参考时钟的时钟和数据恢复电路以及恢复电路和数据的方法，其中时钟和数据恢复电路包括时钟产生单元，镜像延迟单元，前导码相位检测单元和采样 单元。 时钟生成单元生成时钟信号，使得时钟信号的相位被锁定到输入到时钟生成单元的数据信号的相位。 镜像延迟单元在前导码周期期间基于前导信号输出多个延迟前导信号。 前导码相位检测单元在前导码周期期间为电荷泵提供具有关于前导信号和时钟信号之间的相位差的信息的前导码相位检测信号。 采样单元通过采用时钟信号对数据信号进行采样从数据信号中提取数据。