公开(公告)号：US06961280B1

公开(公告)日：2005-11-01

申请号：US10731279

申请日：2003-12-08

申请人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Johnson Tan

发明人： Philip Pan ,  Chiakang Sung ,  Joseph Huang ,  Yan Chong ,  Johnson Tan

IPC分类号： G06F12/08 ,  G11C8/00 ,  G11C8/06 ,  G11C8/10

CPC分类号： G11C8/06 ,  G06F12/0895 ,  G11C8/10

摘要： Techniques are provided for recycling addresses in memory blocks. Address signals in memory blocks are stored temporarily in a set of parallel coupled address registers. The address registers transfer the address signals to an address decoder block, which decodes the address signals. The address decoder block transfers the decoded addresses to a memory array. A stall state occurs when the cache memory block needs a new set of data to replace the old set of data. Address signals are stored in the address registers during the stall state by coupling each register's output to its data input using a series of multiplexers. The multiplexers are controlled by an address stall signal that indicates the onset and the end of a stall state. After the end of a stall state, the address registers store the next address signal received at the memory block.

摘要翻译： 提供技术来回收内存块中的地址。 存储器块中的地址信号被临时存储在一组并行耦合的地址寄存器中。 地址寄存器将地址信号传送到地址解码块，对地址信号进行解码。 地址解码器块将解码的地址传送到存储器阵列。 当缓存存储块需要一组新的数据来替换旧的数据集时，会发生停顿状态。 通过使用一系列多路复用器将每个寄存器的输出耦合到其数据输入，地址信号在失速状态下存储在地址寄存器中。 多路复用器由指示失速状态的开始和结束的地址停止信号控制。 在停止状态结束后，地址寄存器存储在存储块处接收的下一个地址信号。

公开(公告)号：US06912164B1

公开(公告)日：2005-06-28

申请号：US10646538

申请日：2003-08-22

申请人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Philip Pan ,  Johnson Tan

发明人： Yan Chong ,  Chiakang Sung ,  Joseph Huang ,  Philip Pan ,  Johnson Tan

IPC分类号： G11C7/00 ,  G11C7/20

CPC分类号： G11C7/20

摘要： Techniques for preloading data into memory blocks on a programmable circuit are provided. Memory blocks on the a programmable circuit each have dedicated circuitry that loads data into the memory block. The dedicated circuit also generates memory addresses used to load the data into the memory block. The dedicated circuitry associated with each memory block reduces demand on the routing resources. A user can preload data into the memory blocks prior to user mode. A user can also prevent data from being preloaded into one or more of the memory blocks prior to user mode. By allowing the user to program some or all of the memory blocks prior to user mode, the time needed to a program the memory blocks prior to user mode can be substantially reduced.

摘要翻译： 提供了将数据预加载到可编程电路上的存储器块中的技术。 可编程电路上的存储器块都具有将数据加载到存储器块中的专用电路。 专用电路还生成用于将数据加载到存储器块中的存储器地址。 与每个存储器块相关联的专用电路减少对路由资源的需求。 用户可以在用户模式之前将数据预加载到存储器块中。 用户还可以防止在用户模式之前将数据预加载到一个或多个存储器块中。 通过允许用户在用户模式之前对一些或全部存储器块进行编程，可以显着减少用户模式之前存储器块的程序所需的时间。

公开(公告)号：US07057962B1

公开(公告)日：2006-06-06

申请号：US10806638

申请日：2004-03-22

申请人： Johnson Tan ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Joseph Huang

发明人： Johnson Tan ,  Chiakang Sung ,  Philip Pan ,  Yan Chong ,  Joseph Huang

IPC分类号： G11C8/00

CPC分类号： G11C7/1075

摘要： A memory cell of a programmable device includes a memory partitioning circuit to partition a multiple port memory device into one or more single port memory partitions. The memory partitioning circuit prevents cross addressing by setting the value of one or more address lines of each memory port to a fixed value. The memory partitioning circuit holds address lines at their required values during the programmable device's normal, clear, and reset modes of operation. The behavior of the memory partitioning circuit is set by a portion of a device configuration used to configure the programmable device. The memory partitioning circuit is connected between a memory cell's address register and row or column decoders used to access the multiple port memory device. The memory partitioning circuit can also perform bit-wise inversion operations on portions of the memory addresses.

摘要翻译： 可编程设备的存储单元包括用于将多端口存储器设备分割成一个或多个单端口存储器分区的存储器分配电路。 存储器分配电路通过将每个存储器端口的一个或多个地址线的值设置为固定值来防止交叉寻址。 存储器分配电路在可编程器件的正常，清零和复位操作模式期间将地址线保持在其所需的值。 存储器分配电路的行为由用于配置可编程器件的器件配置的一部分来设置。 存储器分配电路连接在存储单元的地址寄存器和用于访问多端口存储器件的行或列解码器之间。 存储器分配电路还可以对存储器地址的部分执行逐位反转操作。

公开(公告)号：US07589556B1

公开(公告)日：2009-09-15

申请号：US11925717

申请日：2007-10-26

申请人： Johnson Tan ,  Andrew Bellis ,  Philip Clarke ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu ,  Chiakang Sung

发明人： Johnson Tan ,  Andrew Bellis ,  Philip Clarke ,  Yan Chong ,  Joseph Huang ,  Michael H. M. Chu ,  Chiakang Sung

IPC分类号： G06F7/38

CPC分类号： H03M9/00 ,  H03K5/131 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00058

摘要： Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.

摘要翻译： 用于动态控制校准数据的电路，方法和装置，用于调整集成电路上的输入和输出信号的时序。 该动态控制允许输入和输出电路通过以有效的方式补偿温度和电压变化而进行自校准，而不需要对器件重新配置。 加载新的校准设置时，可以保持校准设置。 可以减少时钟和数据信号之间以及多个数据信号之间的偏移。 实现动态控制，同时仅消耗包括路由路径在内的最小资源。