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    Method of fabricating complementary bipolar transistors with SiGe base regions
    3.
    发明申请
    Method of fabricating complementary bipolar transistors with SiGe base regions 有权
    用SiGe基极区制造互补双极晶体管的方法

    公开(公告)号：US20050014341A1

    公开(公告)日：2005-01-20

    申请号：US10822078

    申请日：2004-04-08

    申请人： Badih El-Kareh ,  Scott Balster ,  Philipp Steinmann ,  Thomas Scharnagl ,  Manfred Schiekofer ,  Carl Willis

    发明人： Badih El-Kareh ,  Scott Balster ,  Philipp Steinmann ,  Thomas Scharnagl ,  Manfred Schiekofer ,  Carl Willis

    IPC分类号： H01L21/331 ,  H01L21/8228

    CPC分类号： H01L29/66242 ,  H01L21/82285

    摘要： In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.

    摘要翻译： 在制造具有SiGe基极区域的互补双极晶体管的方法中，NPN和PNP晶体管的基极区域通过晶体硅 - 锗层32a，36a的外延沉积而在两个集电极区域20,14之间一个接一个地形成。 使用这种方法，可以自由地为NPN和PNP晶体管选择SiGe层的锗分布，从而可以单独优化互补晶体管的性能。 SiGe层32a，36a可以在硅 - 锗层32a，36a沉积期间或之后掺杂n型或p型掺杂剂。

    Method of fabricating complementary bipolar transistors with SiGe base regions
    4.
    发明授权
    Method of fabricating complementary bipolar transistors with SiGe base regions 有权
    用SiGe基极区制造互补双极晶体管的方法

    公开(公告)号：US07144789B2

    公开(公告)日：2006-12-05

    申请号：US10822078

    申请日：2004-04-08

    申请人： Badih El-Kareh ,  Scott Balster ,  Philipp Steinmann ,  Thomas Scharnagl ,  Manfred Schiekofer ,  Carl Willis

    发明人： Badih El-Kareh ,  Scott Balster ,  Philipp Steinmann ,  Thomas Scharnagl ,  Manfred Schiekofer ,  Carl Willis

    IPC分类号： H01L21/8222

    CPC分类号： H01L29/66242 ,  H01L21/82285

    摘要： In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regions 20, 14 by epitaxial deposition of crystalline silicon-germanium layers 32a, 36a. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layers 32a, 36a can be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers 32a, 36a.

    摘要翻译： 在制造具有SiGe基极区域的互补双极晶体管的方法中，NPN和PNP晶体管的基极区域通过外延沉积晶体硅 - 锗层32a，36a而一个接一个地在两个集电极区域20,14之间形成。 使用这种方法，可以自由地为NPN和PNP晶体管选择SiGe层的锗分布，从而可以单独优化互补晶体管的性能。 SiGe层32a，36a可以在硅 - 锗层32a，36a沉积期间或之后掺杂n型或p型掺杂剂。

    Method of Fabricating an Integrated Circuit with Gate Self-Protection, and an Integrated Circuit with Gate Self-Protection
    5.
    发明申请
    Method of Fabricating an Integrated Circuit with Gate Self-Protection, and an Integrated Circuit with Gate Self-Protection 有权
    具有栅极自保护的集成电路的制造方法以及具有栅极自保护的集成电路

    公开(公告)号：US20070057281A1

    公开(公告)日：2007-03-15

    申请号：US11470760

    申请日：2006-09-07

    申请人： Badih El-Kareh ,  Scott Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

    发明人： Badih El-Kareh ,  Scott Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

    IPC分类号： H01L29/74

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0705

    摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.

    摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。

    Control of dopant diffusion from buried layers in bipolar integrated circuits
    7.
    发明授权
    Control of dopant diffusion from buried layers in bipolar integrated circuits 有权
    控制双极集成电路中埋层的掺杂剂扩散

    公开(公告)号：US08247300B2

    公开(公告)日：2012-08-21

    申请号：US12627794

    申请日：2009-11-30

    申请人： Jeffrey A. Babcock ,  Angelo Pinto ,  Manfred Schiekofer ,  Scott G. Balster ,  Gregory E. Howard ,  Alfred Hausler

    发明人： Jeffrey A. Babcock ,  Angelo Pinto ,  Manfred Schiekofer ,  Scott G. Balster ,  Gregory E. Howard ,  Alfred Hausler

    IPC分类号： H01L21/8222

    CPC分类号： H01L29/66265 ,  H01L21/82285 ,  H01L29/66242 ,  H01L29/7317 ,  H01L29/7378

    摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.

    摘要翻译： 公开了一种集成电路及其制造方法。 集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。 含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。 扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延层中，或通过离子注入形成。 在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。 还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。

    Control of dopant diffusion from buried layers in bipolar integrated circuits
    8.
    发明申请
    Control of dopant diffusion from buried layers in bipolar integrated circuits 审中-公开
    控制双极集成电路中埋层的掺杂剂扩散

    公开(公告)号：US20050250289A1

    公开(公告)日：2005-11-10

    申请号：US11180457

    申请日：2005-07-13

    申请人： Jeffrey Babcock ,  Angelo Pinto ,  Manfred Schiekofer ,  Scott Balster ,  Gregory Howard ,  Alfred Hausler

    发明人： Jeffrey Babcock ,  Angelo Pinto ,  Manfred Schiekofer ,  Scott Balster ,  Gregory Howard ,  Alfred Hausler

    IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L21/8228 ,  H01L29/73 ,  H01L29/737

    CPC分类号： H01L29/66265 ,  H01L21/82285 ,  H01L29/66242 ,  H01L29/7317 ,  H01L29/7378

    摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.

    摘要翻译： 公开了一种集成电路及其制造方法。 集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。 含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。 扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延形成中，或通过离子注入来形成。 在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。 还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。

    CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS
    9.
    发明申请
    CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS 有权
    双极性集成电路中碲化镓的掺杂扩散控制

    公开(公告)号：US20100279481A1

    公开(公告)日：2010-11-04

    申请号：US12627794

    申请日：2009-11-30

    申请人： Jeffrey A. Babcock ,  Angelo Pinto ,  Manfred Schiekofer ,  Scott G. Balster ,  Gregory E. Howard ,  Alfred Hausler

    发明人： Jeffrey A. Babcock ,  Angelo Pinto ,  Manfred Schiekofer ,  Scott G. Balster ,  Gregory E. Howard ,  Alfred Hausler

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66265 ,  H01L21/82285 ,  H01L29/66242 ,  H01L29/7317 ,  H01L29/7378

    摘要： An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (30, 50, 60), each having a buried collector region (26′). A carbon-bearing diffusion barrier (28c) is disposed over the buried collector region (26′), to inhibit the diffusion of dopant from the buried collector region (26′) into the overlying epitaxial layer (28). The diffusion barrier (28c) may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (28), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks (52, 62) may be used to define the locations of the buried collector regions (26′) that are to receive the carbon; for example, portions underlying eventual collector contacts (33, 44c) may be masked from the carbon implant so that dopant from the buried collector region (26′) can diffuse upward to meet the contact (33). MOS transistors (70, 80) including the diffusion barrier (28) are also disclosed.

    摘要翻译： 公开了一种集成电路及其制造方法。 集成电路包括垂直双极晶体管（30,50,60），每个具有一个埋设集电极区域（26'）。 含碳扩散阻挡层（28c）设置在掩埋集电极区域（26'）之上，以阻止掺杂剂从掩埋的集电极区域（26'）扩散到上覆的外延层（28）中。 扩散阻挡层（28c）可以通过将碳源引入上覆层（28）的外延层中，或通过离子注入形成。 在碳或SiGeC的离子注入的情况下，可以使用掩模（52,62）来限定待接收碳的掩埋收集器区域（26'）的位置; 例如，最终的集电极触点（33,44c）下面的部分可以从碳注入掩模，使得来自掩埋的集电极区域（26'）的掺杂剂可向上扩散以满足触点（33）。 还公开了包括扩散阻挡层（28）的MOS晶体管（70,80）。

    Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection
    10.
    发明授权
    Method of fabricating an integrated circuit with gate self-protection, and an integrated circuit with gate self-protection 有权
    具有栅极自保护的集成电路的制造方法和具有栅极自保护的集成电路

    公开(公告)号：US07772057B2

    公开(公告)日：2010-08-10

    申请号：US11470760

    申请日：2006-09-07

    申请人： Badih El-Kareh ,  Scott Gerard Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

    发明人： Badih El-Kareh ,  Scott Gerard Balster ,  Hiroshi Yasuda ,  Manfred Schiekofer

    IPC分类号： H01L21/337

    CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0705

    摘要： An integrated circuit with gate self-protection comprises a MOS device and a bipolar device, wherein the integrated circuit further comprises a semiconductor layer with electrically active regions in which and on which the MOS device and the bipolar device are formed and electrically inactive regions for isolating the electrically active regions from each other. The MOS device comprises a gate structure and a body contacting structure, wherein the body contacting structure is formed of a base layer deposited in a selected region over an electrically active region of the semiconductor layer, and the body contacting structure is electrically connected with the gate structure. The base layer forming the body contacting structure also forms the base of the bipolar device. The present invention further relates to a method for fabricating such an integrated circuit.

    摘要翻译： 具有栅极自保护的集成电路包括MOS器件和双极器件，其中所述集成电路还包括具有电活性区域的半导体层，在其上形成MOS器件和双极器件，并且在其上形成用于隔离的电无活性区域 电活性区域彼此。 MOS器件包括栅极结构和体接触结构，其中所述体接触结构由沉积在所述半导体层的电活性区域上的选定区域中的基底层形成，并且所述体接触结构与所述栅极电连接 结构体。 形成身体接触结构的基层也形成双极器件的基部。 本发明还涉及一种用于制造这种集成电路的方法。