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1.发明授权Electronic device for regulating a variable capacitance of an integrated circuit 有权用于调节集成电路的可变电容的电子装置公开(公告)号：US08692612B2
公开(公告)日：2014-04-08
申请号：US12891409
申请日：2010-09-27
CPC分类号： H03H5/12
摘要： The present disclosure relates to an electronic regulation device of a variable capacitance of an integrated circuit having a time parameter depending on the variable capacitance. The regulation device includes a regulation loop, and is configured to generate in output a plurality of binary regulation signals.
摘要翻译： 本公开涉及具有取决于可变电容的时间参数的集成电路的可变电容的电子调节装置。 调节装置包括调节回路，并且被配置为在输出中产生多个二进制调节信号。
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公开(公告)号：US4883993A
公开(公告)日：1989-11-28
申请号：US279036
申请日：1988-12-02
IPC分类号： H03K5/1252
CPC分类号： H03K5/1252
摘要： The antibounce circuit comprises:(a) a first flip-flop constituted by a first and a second NAND gate (10, 12) having their respective outputs connected to one of the inputs of the other gate, the free input of the first gate being the input for said digital signal;(b) a second flip-flop constituted by a third and fourth NAND gate (14, 16) having their respective outputs connected to one of the inputs of the other gate, the free input of the third gate being connected to the output of the first gate;(c) a non-inverting delay circuit (20, 22, 24) connecting the output of the third gate to the free input of the second gate;(d) a first inverter connecting the output of the delay circuit to the free input of the fourth gate.
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3.发明授权Circuit for reconstructing an analog signal from a digital signal and transmission system, particularly for WCDMA cellular telephony, including such circuit 有权用于重建来自数字信号和传输系统的模拟信号的电路，特别是用于包括这种电路的WCDMA蜂窝电话公开(公告)号：US07400285B2
公开(公告)日：2008-07-15
申请号：US11569630
申请日：2005-05-19
IPC分类号： H03M1/66
CPC分类号： H04B1/707
摘要： A circuit for reconstructing an analog signal starting from a digital input signal includes a digital to analog converter and a low pass-filter connected at the output of the converter for receiving the analog format signal and outputting a reconstructed analog signal. The low pass filter is an active filter continuous in time and current-coupled to the output of the digital-analog converter. The digital-analog converter is of the current-steering type functioning at a sampling frequency greater than the Nyquist frequency of the analog signal.
摘要翻译： 用于重建从数字输入信号开始的模拟信号的电路包括数模转换器和连接在转换器输出端的低通滤波器，用于接收模拟格式信号并输出重构的模拟信号。 低通滤波器是时间上连续的有源滤波器，并且与数模转换器的输出电流耦合。 数模转换器是以大于模拟信号的奈奎斯特频率的采样频率工作的电流导向型。
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4.发明申请Circuit For Reconstructing an Analog Signal From a Digital Signal and Transmission System, Particularly For Wcdma Cellular Telephony, Including Such Circuit 有权用于从数字信号和传输系统重建模拟信号的电路，特别是用于Wcdma蜂窝电话，包括此类电路公开(公告)号：US20070262894A1
公开(公告)日：2007-11-15
申请号：US11569630
申请日：2005-05-19
CPC分类号： H04B1/707
摘要： There is described a circuit for reconstructing an analog signal from a digital signal and wide-band transmission system, particularly for employment in cellular telephony systems, or more in general in mobile communication systems, that adopt the WCDMA standard. The circuit comprises: a digital to analog converter (DAC) suitable for receiving said digital signal and converting it into signal in analog.format;—a low pass-filter (LOW-PASS) connected at the output of said converter for receiving said signal in analog format and providing as output said reconstructed analog signal. Advantageously, the low pass filter (LOW-PASS) is an active filter continuous in time and current coupled to the output of the digital-analog converter (DAC) and the digital-analog converter (DAC) is a converter of the current-steering type functioning at sampling frequency greater than the Nyquist frequency of said analog signal to be reconstructed.
摘要翻译： 描述了一种用于从数字信号和宽带传输系统重建模拟信号的电路，特别是用于蜂窝电话系统中的用途，或更一般地在采用WCDMA标准的移动通信系统中。 该电路包括：适于接收所述数字信号并将其转换成模拟信号的数模转换器（DAC）; - 在所述转换器的输出处连接的低通滤波器（低通滤波器），用于接收所述信号 以模拟格式提供并提供所述重构的模拟信号作为输出。 有利地，低通滤波器（LOW-PASS）是连续的数字模拟转换器（DAC）的输出端的时间和电流连续的有源滤波器，并且数模转换器（DAC）是电流转向器 在大于待重构的所述模拟信号的奈奎斯特频率的采样频率下工作。
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5.发明授权公开(公告)号：US06940348B2
公开(公告)日：2005-09-06
申请号：US10471807
申请日：2002-07-05
CPC分类号： H03F3/45937 , H03F1/303
摘要： The circuit comprises a differential amplifier with two inputs and two outputs and a common mode regulation circuit. Between a regulation terminal of the amplifier and the outputs there are connected first and second capacitors and first and second capacitive elements that by controlled switches are connected in parallel with, respectively, the first and second capacitors or alternately between first and second reference voltage terminals. The common mode output voltage is not exactly fixed at the beginning of the design, but is determined by attributing appropriate values to the first and second capacitive elements; more particularly, their capacitances C3 and C4 are chosen in such a way as to satisfy the following equality: Vcmn=Vrefl+[(Vrefp−Vrefm)/2]*(C4−C3)/(C3+C4), where Vcmn is the desired common mode output voltage, Vrefp and Vrefm are the differential output voltages and Vrefl is the voltage of the second reference terminal.
摘要翻译： 该电路包括具有两个输入和两个输出的差分放大器和一个共模调节电路。 在放大器的调节端子和输出端之间，连接有第一和第二电容器以及通过受控开关分别与第一和第二电容器或第一和第二参考电压端子并联连接的第一和第二电容元件。 共模输出电压在设计开始时不是完全固定的，而是通过将适当的值归因于第一和第二电容元件来确定的; 更具体地说，它们的电容C3和C4以满足以下等式的方式选择：<？in-line-formula description =“In-line formula”end =“lead”？> Vcmn = Vrefl + [（Vrefp- Vrefm）/ 2] *（C 4 -C 3）/（C 3 + C 4），<？in-line-formula description =“In-line formula”end =“tail”？>其中Vcmn是所需的公共 模式输出电压，Vrefp和Vrefm是差分输出电压，Vrefl是第二参考端子的电压。
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公开(公告)号：US5617055A
公开(公告)日：1997-04-01
申请号：US509304
申请日：1995-07-31
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/092 , H03K17/687 , H03K17/62
CPC分类号： H03K17/6872 , H03K2217/0018
摘要： An electronic switch having a reduced body effect includes first and second switch terminals. A first transistor of a first type has a control terminal, a first substrate coupled to a first voltage level, and first and second drive terminals respectively coupled to the first and second switch terminals. A second transistor of a second type has a control terminal, a second substrate, a first drive terminal coupled to the second substrate and to the first switch terminal, and a second drive terminal. A third transistor of the second type has a control terminal, a third substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the third substrate and to the second switch terminal. A fourth transistor of a first type has a control terminal, a fourth substrate, a first drive terminal coupled to the second drive terminal of the second transistor, and a second drive terminal coupled to the fourth substrate and a first voltage level.
摘要翻译： 具有减小的身体效应的电子开关包括第一和第二开关端子。 第一类型的第一晶体管具有控制端子，耦合到第一电压电平的第一衬底以及分别耦合到第一和第二开关端子的第一和第二驱动端子。 第二类型的第二晶体管具有控制端子，第二基板，耦合到第二基板和第一开关端子的第一驱动端子和第二驱动端子。 第二类型的第三晶体管具有控制端子，第三基板，耦合到第二晶体管的第二驱动端子的第一驱动端子和耦合到第三基板和第二开关端子的第二驱动端子。 第一类型的第四晶体管具有控制端子，第四衬底，耦合到第二晶体管的第二驱动端子的第一驱动端子和耦合到第四衬底的第二驱动端子和第一电压电平。
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7.发明授权
公开(公告)号：US5559687A
公开(公告)日：1996-09-24
申请号：US261473
申请日：1994-06-17
CPC分类号： H02M3/07
摘要： A voltage multiplier for relatively high output current has its design output voltage stabilized and rendered independent of process spread, temperature, supply voltage and output current level, by a stabilization loop driving the switch that cyclically connects to ground a charge transfer capacitance of the functional voltage multiplier circuit. The feedback loop comprises an integrating stage, stabilized by creating a low-frequency zero in the transfer function for compensating one of two low-frequency poles of the transfer function of the whole circuit.
摘要翻译： 用于相对较高输出电流的电压倍增器，其设计输出电压稳定并且独立于工艺扩展，温度，电源电压和输出电流电平，通过稳定环路驱动开关，循环地连接到接地的功能电压的电荷转移电容 乘法器电路。 反馈回路包括积分级，通过在传递函数中产生低频零点来稳定，以补偿整个电路的传递函数的两个低频极点中的一个。
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公开(公告)号：US07986181B2
公开(公告)日：2011-07-26
申请号：US12035235
申请日：2008-02-21
IPC分类号： H03K5/00
CPC分类号： H03H7/0153 , H03H1/02 , H03H2210/021 , H03H2210/043
摘要： A calibration circuit for calibrating an adjustable capacitance of a circuit having a time constant depending on the adjustable capacitance, the calibration circuit generating a calibration signal for calibrating the capacitance and including a calibration loop, suitable to carry out a calibration cycle in several sequential steps. The calibration circuit includes a controllable capacitance for receiving a control signal and including an array of switched capacitors selectively activated by the control signal to connect to a first common node that conducts a voltage value depending on the total capacitance value of the activated capacitors; an assessment unit for comparing this voltage value with a reference voltage to output a logic signal that can transition between first and second logic levels; a control and timing unit to receive the logic signal and change the control signal to carry out a subsequent calibration step that is provided at the end of the integration interval during a comparison interval of a preset duration, which allows a transition of the logic signal to occur prior to the beginning of the consecutive calibration step.
摘要翻译： 一种用于校准具有取决于可调电容的时间常数的电路的可调电容的校准电路，所述校准电路产生用于校准电容的校准信号，并且包括适于在几个连续步骤中执行校准循环的校准环路。 校准电路包括用于接收控制信号并包括由控制信号选择性激活的开关电容阵列的可控电容，以连接到第一公共节点，该第一公共节点根据所激活的电容器的总电容值传导电压值; 评估单元，用于将该电压值与参考电压进行比较，以输出可在第一和第二逻辑电平之间转换的逻辑信号; 控制和定时单元，用于接收逻辑信号并改变控制信号，以执行在预设持续时间的比较间隔期间在积分间隔结束时提供的随后的校准步骤，这允许将逻辑信号转换为 在连续校准步骤开始之前发生。
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公开(公告)号：US07098831B2
公开(公告)日：2006-08-29
申请号：US10791663
申请日：2004-03-02
IPC分类号： H03M1/66
摘要： A digital-to-analog converter includes a first section (MSB) that converts the more significant bits of a digital code into a first voltage (Vin) of a multiplicity of discrete voltages that are integral multiples of a predetermined first voltage step (ΔV1). A second section (LSB) of the converter converts the less significant bits of the digital code into a current. The current is transformed into a second voltage of a multiplicity of discrete voltages that are integral multiples of a second voltage step (ΔV2) equal to ½L of the product of the first voltage step (ΔV1) multiplied by a predetermined coefficient, where L is the number of the less significant bits of the digital code to be converted. A summer generates an output voltage (Vout) that is the sum of the second voltage and the product of the first voltage multiplied by the predetermined coefficient. With a view to obtaining a low consumption, the summer has a resistive feedback circuit including a voltage divider (R3, R4). A conversion resistor (R4) that forms part of the voltage divider transforms the current into the second voltage.
摘要翻译： 数模转换器包括第一部分（MSB），其将数字代码的更高有效位转换为多个离散电压的第一电压（Vin），所述多个离散电压是预定的第一电压步长（DeltaV 1 ）。 转换器的第二部分（LSB）将数字代码的较低有效位转换为电流。 将电流转换成多个离散电压的第二电压，其是等于第一电压阶跃（ΔV1）乘以预定系数的乘积的1/2L的第二电压阶跃（ΔV2）的整数倍的倍数，其中L 是要转换的数字代码的较低有效位的数量。 夏天产生作为第一电压乘以预定系数的第二电压和乘积之和的输出电压（Vout）。 为了获得低消耗，夏季具有包括分压器（R 3，R 4）的电阻反馈电路。 形成分压器一部分的转换电阻器（R 4）将电流转换成第二电压。
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10.发明授权Digital system with an output buffer with a switching current settable to load-independent constant values 有权具有输出缓冲器的数字系统，其开关电流可设置为负载无关常数公开(公告)号：US06914457B2
公开(公告)日：2005-07-05
申请号：US10460035
申请日：2003-06-10
CPC分类号： H03K17/166 , H03K17/164
摘要： A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.
摘要翻译： 数字系统包括数字数据处理单元，连接到处理单元的至少一个输出缓冲器，以响应于从处理单元到达的数字信号产生输出信号，并且至少一个用户单元作为输出缓冲器负载进行连接。 为了确保输出缓冲器的开关电流可以被设置为不同的值，输出缓冲器包括用于将开关电流固定为基本上恒定且与负载无关的值的装置和用于选择性地设置 开关电流和处理单元包括用于存储预定参数的装置; 所述装置连接到选择设定装置，用于将切换电流的值设定为预定参数的函数。
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